SiC JFET Gate Width Control via Sidewall Spacers
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Solution Overview
Problem
Conventional methods for manufacturing trench-type junction field effect transistors (JFETs) on silicon carbide (SiC) substrates face challenges in accurately controlling the interval between adjacent gate regions and impurity concentration profiles, leading to difficulties in reducing on-resistance and maintaining high yield and withstand voltage, especially due to limitations in oblique ion implantation methods.
Innovation Solution
The method involves forming shallow trenches in the SiC substrate with a vertical ion implantation technique to create n-type and p-type gate layers, using sidewall spacers to self-align the p-type gate formation, and optimizing the impurity concentration profiles to achieve a narrower gate width and improved dimensional accuracy, thereby increasing the source area ratio and reducing on-resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the interval between adjacent gate regions is increased to reduce on-resistance, then the on-resistance decreases, but the source and drain withstand voltages at reverse bias decrease
Solution Approach 1:
The patent applies local quality by creating different impurity concentration profiles in different regions of the gate. Specifically, the impurity concentration is made higher near the channel region and lower toward the source/drain regions, achieving a stepped or graded profile. This localized variation in impurity concentration allows the gate to provide effective field control for low on-resistance while maintaining adequate breakdown voltage through the higher concentration regions near the channel.
2Reliability
If the impurity concentration profile of the p-type gate region is made steep to improve the tradeoff between on-resistance and withstand voltages, then the performance improves, but the manufacturing complexity increases due to multiple parameters to control
Solution Approach 1:
The patent applies preliminary action by forming sidewall spacers on the trench walls before performing ion implantation to create the p-type gate region. These spacers serve as masks that automatically define the implantation regions and concentrations. By preparing this spacer structure in advance, the complex stepped impurity profile is achieved through a standardized sequence of deposition and implantation steps, reducing the need for multiple separate masking and implantation operations.
3Manufacturing precision
If the width of the p-type gate region is reduced to increase the source area ratio and reduce on-resistance, then the on-resistance decreases, but the dimensional control accuracy becomes more difficult to achieve
Solution Approach 1:
The patent applies self-service by using the sidewall spacers themselves as the defining structure for the gate region width. The spacers are formed by depositing material on the trench sidewalls, and their thickness directly determines the gate region dimensions. This self-aligned approach eliminates the need for separate photolithography alignment steps, and the dimensional control is achieved through controlled deposition thickness rather than optical alignment, providing better precision for narrow dimensions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the production of high-performance JFETs with improved on-resistance and withstand voltage, enhanced current density, and reduced leakage current, while ensuring stable high yields and process margins.
Implementation Method 1
forming shallow trenches in the SiC substrate with a vertical ion implantation technique to create n-type and p-type gate layers
Data Source
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AI summary
A manufacturing method of a junction field effect transistor includes the steps of: (a) forming an n+-type source layer on a surface of an n--type drift layer formed on an n+-type SiC substrate; (b) forming a plurality of shallow trenches disposed at predetermined intervals by etching the surface of the n--type drift layer with a silicon oxide film formed on the n--type drift layer used as a mask; (c) forming an n-type counter dope layer by doping the n--type drift layer below each of the shallow trenches with nitrogen by using a vertical ion implantation method; (d) forming a sidewall spacer on each sidewall of the silicon oxide film and the shallow trenches; and (e) forming a p-type gate layer by doping the n- -type drift layer below each of shallow trenches with aluminum by using the vertical ion implantation method.