SiC JFET Level-Shifting Circuit With Low Temperature Sensitivity
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Solution Overview
Problem
Existing JFET circuits face limitations in voltage and temperature sensitivity, as increasing supply voltage does not effectively compensate for temperature variations, leading to unstable logic circuit performance.
Innovation Solution
The solution involves moving resistors to the input stage and using diode degenerated JFET sources in the output stage, which compensates for voltage and temperature sensitivities, resulting in low temperature sensitivity and improved gain through the use of integrated-series forward-biased JFET gate-to-channel diode junctions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If supply voltage is increased to compensate for temperature variations, then logic circuit performance stability improves, but device complexity and sensitivity to voltage changes worsen
Solution Approach 1:
The circuit uses self-complementary JFET pairs where one device naturally compensates for the temperature drift of the other without requiring external voltage adjustment mechanisms. The symmetric configuration allows the circuit to self-regulate its operating point across temperature variations.
Solution Approach 2:
The invention changes the operating parameters by using complementary JFET devices with opposite temperature coefficients. By biasing both devices and utilizing their opposing drift characteristics, the circuit achieves temperature compensation through parameter cancellation rather than voltage scaling.
2Power
If resistors are placed in the output stage, then gain is improved, but temperature sensitivity increases
Solution Approach 1:
The invention extracts the temperature-sensitive resistive elements from the output stage and relocates them to the input stage where they are part of the symmetric biasing network. This extraction eliminates the harmful temperature sensitivity from the gain-determining output section while preserving the beneficial gain characteristics.
Solution Approach 2:
The patent employs asymmetric device pairing with complementary JFETs having opposite temperature coefficients. This asymmetric approach allows the output stage to achieve high gain through device transconductance rather than resistive loading, thereby avoiding temperature sensitivity while maintaining amplification capability.
3Ease of operation
If JFET threshold voltage is shifted towards enhancement mode, then pull-up capability is enhanced, but manufacturing precision requirements increase
Solution Approach 1:
The circuit uses complementary JFET pairs where devices with opposite threshold voltage characteristics are paired together. The negative threshold drift of one device counterweights the positive threshold drift of its complement, achieving stable pull-up capability without requiring ultra-precise threshold voltage control during manufacturing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the pull-up capability of the output stage, achieving symmetrical rise and fall times and shifting the JFET's threshold voltage towards enhancement mode with reduced temperature sensitivity, thereby stabilizing logic circuit performance.
Implementation Method 1
integrated-series forward-biased JFET gate-to-channel diode junctions
Data Source
AI summary
An improved electrical circuit for logic output level shifting using SiC JFETs with resistors on the input, inverting, stage and using diode degenerated JFET sources in the output stage.