SiC Vertical JFET Mask Reduction via Self-Aligned Silicide Contacts
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Solution Overview
Problem
The existing processes for manufacturing vertical junction field-effect transistors (JFETs) from silicon carbide (SiC) are complex and costly due to the need for multiple masks, which complicates the formation of mesas, trenches, and metallization, and does not allow for efficient variation in trench and mesa widths between active and termination regions.
Innovation Solution
A simplified process using a limited number of masks to form mesas and trenches simultaneously, followed by a mask-less self-aligned process for silicide source and gate contacts, and separate masks for patterning metallization and passivation, allowing optional angled doping and variation in trench and mesa widths between active and termination regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple masks are used to form mesas, trenches, and metallization separately, then manufacturing precision is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent combines the formation of mesas and trenches into a single etching process using one mask pattern, rather than requiring separate masks for each feature. This merging of operations reduces the total number of masks needed while maintaining the precision of feature formation through the unified pattern design.
Solution Approach 2:
The mask design serves multiple functions simultaneously: it defines both mesa and trench locations, establishes alignment references for subsequent processing steps, and enables self-aligned contact formation. This multi-functionality reduces the overall mask set complexity while maintaining manufacturing precision.
2Manufacturing precision
If multiple masks are used for metallization patterning, then manufacturing precision is improved, but manufacturing cost increases
Solution Approach 1:
The patent combines metallization patterning with contact window formation into a single masking and etching operation. The same mask that defines contact locations also defines metallization regions, eliminating the need for separate metallization patterning masks and reducing overall manufacturing cost while maintaining precision.
Solution Approach 2:
The mask pattern itself provides self-alignment features that automatically guide subsequent metallization deposition and patterning steps without requiring additional alignment masks. The mask structures serve as their own alignment references, reducing the number of masks needed and simplifying the manufacturing process.
3Ease of manufacture
If fixed trench and mesa widths are used, then manufacturing simplicity is improved, but adaptability decreases
Solution Approach 1:
The mask pattern incorporates different width specifications for mesas and trenches in different regions (active cell vs. termination regions). This local variation in geometric parameters within the single mask design enables adaptability for different device regions while maintaining the simplicity of a unified masking process.
Solution Approach 2:
The patent introduces width variation as a design parameter within the single mask pattern, allowing different mesa and trench widths in different regions. This dimensional flexibility is achieved through the mask geometry design itself, enabling adaptability without requiring multiple masks or complex process changes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces manufacturing costs and complexity while improving the performance of SiC JFETs by enabling efficient edge terminations and optimized channel doping, enhancing the device's ability to support high voltages and reduce breakdown voltage.
Implementation Method 1
The channel may be doped via one or more angled implantations
Data Source
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AI summary
A vertical JFET made by a process using a limited number of masks. A first mask is used to form mesas and trenches in active cell and termination regions simultaneously. A maskless self-aligned process is used to form silicide source and gate contacts. A second mask is used to open windows to the contacts. A third mask is used to pattern overlay metallization. An optional fourth mask is used to pattern passivation. The channel is doped via angled implantation, and the width of the trenches and mesas in the active cell region may optionally be varied from those in the termination region.