SiC JFET Mesa End Isolation for Lower Leakage Current

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Solution Overview

Problem

Silicon carbide (SiC) junction field effect transistors (JFETs) face challenges due to their normally-on nature and surface roughness issues, which affect reliability and leakage current, particularly at high voltage operations.

Innovation Solution

The method involves forming additional mesa regions at the ends of mesa stripes, which are electrically insulated and separated by trenches, to reduce surface roughness and prevent participation in active device operation, thereby reducing leakage current and enhancing reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of stationary object

If mesa stripes are formed in SiC JFETs to reduce chip area, then device density and integration are improved, but surface roughness at mesa end surfaces increases causing higher leakage current

Engineering Contradiction:
Improvechip areaVSAvoidleakage current
Core Design Contradiction:
Area of stationary objectVSReliability

Solution Approach 1:

The patent extracts the problematic end surfaces of mesa stripes by forming additional mesa regions that extend beyond the active mesa stripes. These additional regions are then electrically insulated through deep level doping, effectively removing the source of surface roughness-induced leakage from the active device operation while preserving the compact mesa stripe structure for high density.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent introduces an intermediary additional mesa region between the active mesa stripe and the substrate/surroundings. This intermediary structure acts as a buffer that captures surface roughness effects through controlled doping, preventing direct interaction between the rough end surfaces and the active device regions, thereby reducing leakage current.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Power

If mesa stripes are formed to achieve high current carrying capability, then power handling is improved, but surface roughness leads to increased leakage current

Engineering Contradiction:
Improvecurrent carrying capabilityVSAvoidleakage current
Core Design Contradiction:
PowerVSObject-generated harmful factors

Solution Approach 1:

The patent converts the harmful surface roughness at mesa end surfaces into a beneficial effect by deliberately forming additional mesa regions with controlled deep level doping. The doping transforms the rough surfaces into electrically insulating regions, turning what would be leakage sources into protective barriers that actually reduce overall device leakage.

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

3Reliability

If additional mesa regions are formed and electrically insulated, then leakage current is reduced, but device structure complexity increases

Engineering Contradiction:
Improveleakage currentVSAvoidstructure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges the formation of additional mesa regions with the existing mesa stripe fabrication process. The additional regions are created using the same etching and doping steps that define the active mesa structures, integrating the leakage reduction feature into the base manufacturing flow without requiring entirely separate process modules.

Inventive Principle:
Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively reduces leakage current and improves the reliability of SiC JFETs by isolating and passivating the end surfaces of mesa stripes, enhancing their performance in high voltage applications.

Implementation Method 1

The method may further include implanting deep level dopant ions into the at least one mesa stripe to form the electrically insulating portion of the at least one mesa stripe

Methodology Applied
Scientific EffectIon implantation: Ion Implantation

Data Source

PatentUS20240145537A1Semiconductor devices with additional mesa structures for reduced surface roughness
Publication Date: 2024.05.02 WOLFSPEED INC
  • US20240145537A1 patent drawing
  • US20240145537A1 patent drawing
  • US20240145537A1 patent drawing

AI summary

A method of forming a semiconductor device includes etching a semiconductor layer to form a plurality of mesa stripes in the semiconductor layer. The plurality of mesa stripes extend in a first direction and include mesa sidewalls that extend in the first direction and mesa surfaces at opposite ends of the mesa stripes. An additional mesa region is formed at an end of at least one of the mesa stripes. The additional mesa region is electrically insulated from the at least one of the mesa stripes. A semiconductor device structure includes a plurality of mesa stripes that extend in a first direction and include mesa sidewalls that extend in the first direction and mesa end surfaces at opposite ends of the mesa stripes. An additional mesa region that is electrically insulated from the at least one of the mesa stripes is at an end of at least one of the mesa stripes.