SiC JFET Gate Formation via Multi-Epitaxial Segmentation
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Solution Overview
Problem
In semiconductor devices, particularly SiC-based JFETs, challenges include precise control of gate region areas, increased junction current due to heavily doped PN junctions, high-energy ion implantation requirements for edge termination, and elevated gate resistance due to electrode wiring constraints.
Innovation Solution
A multi-epitaxial method involving repeated processes of epitaxial growth, ion implantation, and activation annealing is employed to form gate regions with precise gate-to-gate spacing, reducing junction current and gate resistance by using a multi-layered epitaxial structure and optimized ion implantation energies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If ion implantation is performed to form gate regions in SiC-based JFET, then gate regions are formed, but manufacturing precision deteriorates due to difficulty in controlling gate-to-gate spacing
Solution Approach 1:
The gate region formation process is segmented into multiple discrete steps: forming first gate regions through ion implantation, then forming second gate regions through additional ion implantation. This segmentation allows independent optimization and precise control of each gate region's position and dimensions, thereby achieving high manufacturing precision for gate-to-gate spacing while maintaining ease of manufacture through standardized process modules
Solution Approach 2:
The first gate regions are formed in advance through ion implantation before the second gate regions are created. This preliminary action establishes a foundation for subsequent processing steps, allowing precise positioning and spacing control to be built into the structure early in the manufacturing sequence, which simplifies later alignment operations
2Reliability
If heavily doped PN junction is formed between source region and gate region, then junction formation is achieved, but harmful factors increase due to increased junction current
Solution Approach 1:
The doping concentration is optimized locally at the PN junction interface between source and gate regions. By controlling the implantation dose and energy to achieve appropriate doping levels only where needed, the junction is formed with sufficient reliability while minimizing excess carrier generation that would increase junction current
Solution Approach 2:
The doping parameters (concentration, depth, distribution) are precisely controlled through ion implantation energy and dose adjustments. By optimizing these parameters, the PN junction achieves the required electrical characteristics for reliable operation while minimizing harmful junction current through precise parameter management
3Reliability
If high-energy ion implantation is performed for edge termination, then edge termination is achieved, but use of energy increases
Solution Approach 1:
The edge termination process is segmented into multiple ion implantation steps with different energies rather than using a single high-energy step. This allows the implantation profile to be built up in layers, achieving the required termination characteristics while distributing energy input across multiple lower-energy steps
Solution Approach 2:
Multiple ion implantation steps are performed with progressively adjusted energies to achieve the desired edge termination profile. By using partial actions (multiple steps rather than one excessive step), the process achieves reliable edge termination while managing total energy consumption through optimized step-wise implantation
4Ease of manufacture
If electrode wiring is placed immediately above gate region, then wiring layout is simplified, but gate resistance increases due to process constraints
Solution Approach 1:
The gate regions are formed with extended structures in the vertical dimension through multi-step ion implantation, creating protruding portions that extend toward the electrode wiring. This dimensional change allows wiring to be positioned more favorably without increasing lateral spacing, thereby simplifying layout while maintaining low gate resistance through reduced current path length
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables high-precision setting of gate-to-gate spacing, reduces junction current, and lowers gate resistance, enhancing the reliability and performance of SiC-based JFETs by simplifying edge termination and electrode wiring.
Implementation Method 1
epitaxial growth
Implementation Method 2
ion implantation
Implementation Method 3
activation annealing
Data Source
AI summary
In general, in a semiconductor active element such as a normally-off JFET based on SiC in which an impurity diffusion speed is significantly lower than in silicon, gate regions are formed through ion implantation into the side walls of trenches formed in source regions. However, to ensure the performance of the JFET, it is necessary to control the area between the gate regions thereof with high precision. Besides, there is such a problem that, since a heavily doped PN junction is formed by forming the gate regions in the source regions, an increase in junction current cannot be avoided. The present invention provides a normally-off power JFET and a manufacturing method thereof and forms the gate regions according to a multi-epitaxial method which repeats a process including epitaxial growth, ion implantation, and activation annealing a plurality of times.