SiC JFET Source Region Etching Control via PN Junction Detection
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Solution Overview
Problem
The existing method for manufacturing silicon carbide (SiC) semiconductor devices with a junction field effect transistor (JFET) trench structure faces challenges in precisely controlling the removal of the n+ type source region during planarization, leading to inconsistencies in the thickness of the p+ type first gate region, which can result in reduced breakdown voltage.
Innovation Solution
A method is developed where a second concave portion is formed to expose the pn junction between the source and first gate regions, allowing for precise detection and controlled etching of the source region thickness, preventing unnecessary thinning or elimination of the first gate region. This involves selective etching based on SEM observations of the pn junction, ensuring accurate etching depth and maintaining the thickness of the first gate region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the substrate surface is planarized after the n- type channel layer and the p+ type second gate region have epitaxially grown within the trench, then the surface is flattened, but the removal amount of the n+ type source region varies and cannot be precisely controlled
Solution Approach 1:
The patent applies preliminary action by forming a second concave portion before the first concave portion, which exposes the pn junction between the source region and first gate region. This preliminary exposure allows for precise measurement of the source region thickness before the main planarization process, enabling better control over the removal amount during subsequent etching steps.
Solution Approach 2:
The patent uses the pn junction as an intermediary marker to indicate the boundary between the source region and first gate region. By making the pn junction visible through the second concave portion, it serves as a reference point for controlling the etching depth, allowing precise determination of when to stop the planarization process to prevent over-removal of the source region.
2Manufacturing precision
If the n+ type source region is removed excessively during planarization, then the surface is flattened, but the thickness of the p+ type first gate region is thinned or eliminated
Solution Approach 1:
The patent implements feedback control by using the exposed pn junction in the second concave portion as a visual indicator during the planarization process. As the substrate surface is etched, the depth of the first concave portion can be monitored relative to the second concave portion, providing real-time feedback on the removal amount. This allows the process to be stopped at the precise moment when the source region is sufficiently removed without compromising the first gate region thickness.
Solution Approach 2:
The second concave portion is formed in advance to establish a reference depth level that corresponds to the pn junction. This preliminary structure serves as a depth marker that guides the subsequent planarization process, ensuring that the etching stops before reaching the first gate region, thus preventing thinning or elimination of this critical component.
3Volume of moving object
If the thickness of the n+ type source region is small, then the device structure is compact, but it is difficult to grasp the actual removal amount by optical evaluation
Solution Approach 1:
The patent transitions from measuring the source region thickness in a single dimension (direct optical evaluation of the thin layer) to a multi-dimensional approach by creating the second concave portion that exposes the pn junction. This vertical dimension change allows the thickness information to be visualized as a depth difference between the two concave portions, making it detectable through optical microscopy even when the source region itself is too thin for direct measurement.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method enables precise control over the etching process, preventing the thinning or elimination of the first gate region, thereby enhancing the breakdown voltage and improving the manufacturing precision of SiC semiconductor devices.
Implementation Method 1
a second concave portion that configures a second mesa portion in an outer peripheral position of the cell region than a stepped portion of the first mesa portion within the first concave portion
Implementation Method 2
an n− type channel layer and a p+ type second gate region are allowed to epitaxially grow within the trench
Data Source
AI summary
In a method of manufacturing a silicon carbide semiconductor device having a JFET, after forming a second concave portion configuring a second mesa portion, a thickness of a source region is detected by observing a pn junction between the source region and a first gate region exposed by the second concave portion. Selective etching is conducted on the basis of the detection result to form a first concave portion deeper than the thickness of the source region and configuring a first mesa portion inside of an outer peripheral region in an outer periphery of a cell region, and to make the second concave portion deeper than the second gate region.