SiC Semiconductor Device JFET Striped Structure Short-Circuit Protection
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Solution Overview
Problem
There is a trade-off between reducing on-resistance and improving the withstand capacity of SiC semiconductor devices during load short-circuit conditions, making it challenging to achieve both low on-resistance and low saturation current simultaneously.
Innovation Solution
The semiconductor device incorporates a JFET portion with a striped shape, a p-type deep layer, and a specific impurity concentration gradient, which suppresses depletion layer extension and pinches off the JFET portion at higher voltages, thereby achieving low on-resistance and low saturation current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the on-resistance of the semiconductor element is reduced, then the switching loss is reduced, but the saturation current at the time of load short-circuit increases
Solution Approach 1:
The semiconductor device is divided into multiple functional regions: a first conductivity type layer, a second conductivity type region, and a JFET portion with third conductivity type. This segmentation allows each region to perform its specific function - the second conductivity type region provides low on-resistance for reduced switching loss, while the JFET portion with opposite conductivity type acts as a current barrier to limit saturation current during short-circuit conditions.
Solution Approach 2:
Different regions of the semiconductor device are assigned different conductivity types and doping concentrations to optimize local performance. The second conductivity type region has high doping concentration to reduce on-resistance, while the JFET portion has opposite conductivity type to provide current limiting. This local differentiation resolves the contradiction between low on-resistance and low saturation current.
2Productivity
If the on-resistance value becomes smaller, then the switching performance improves, but the withstand capacity at the time of load short-circuit is reduced
Solution Approach 1:
The device structure is segmented into distinct functional zones with different conductivity types. The second conductivity type region enables high-speed switching with low on-resistance, while the JFET portion with third conductivity type (opposite to second) provides a natural current barrier that limits saturation current during short-circuit events, thereby protecting the device and maintaining reliability.
Solution Approach 2:
The JFET portion acts as an intermediary barrier between the high-current switching path and the external circuit. During normal operation, it allows efficient current flow, but during short-circuit conditions, it pinches off to limit the saturation current, thus mediating between the conflicting requirements of high switching performance and high withstand capacity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration allows for reduced on-resistance and improved tolerance during load short-circuit conditions, enhancing the reliability and switching speed of the SiC semiconductor device.
Implementation Method 1
a gate insulation film formed on a channel region that is a part of the second conductivity type region; a gate electrode formed on the gate insulation film
Implementation Method 2
a JFET portion that is formed on the first conductivity type layer, is sandwiched by the second conductivity type region to be placed
Data Source
AI summary
A semiconductor device includes: an inversion type semiconductor element that includes: a substrate having a first conductivity type or a second conductivity type; a first conductivity type layer formed on the substrate; a second conductivity type region that is formed on the first conductivity type layer; a JFET portion that is formed on the first conductivity type layer, is sandwiched by the second conductivity type region to be placed; a source region that is formed on the second conductivity region; a gate insulation film formed on a channel region that is a part of the second conductivity type region; a gate electrode formed on the gate insulation film; an interlayer insulation film covering the gate electrode and the gate insulation film, and including a contact hole; a source electrode electrically connected to the source region through the contact hole; and a drain electrode formed on a back side of the substrate.