SiC JTE Structure Reducing Termination Area
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Solution Overview
Problem
In semiconductor devices with silicon carbide, the presence of positive charge at the interface between silicon carbide and an insulating film leads to variations in breakdown voltage, requiring a wide JTE structure that increases chip size and costs, making it challenging for downsizing and cost reduction in power conversion devices and three-phase motor systems, particularly in automobiles and railway vehicles.
Innovation Solution
A semiconductor device with a JTE structure featuring a constant concentration gradient in the periphery of a silicon carbide p-n diode, reducing the area of the termination structure while maintaining suppressed breakdown voltage variation, achieved by ion-implanting p-type impurities with specific concentrations and widths to avoid avalanche breakdown.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a wide JTE structure is employed to suppress breakdown voltage variation caused by positive charge at the silicon carbide-insulating film interface, then the breakdown voltage stability is improved, but the chip size and manufacturing cost increase
Solution Approach 1:
The patent applies local quality by creating a JTE structure with spatially varying impurity concentrations. Specifically, it forms a first JTE region with a first impurity concentration and a second JTE region with a second impurity concentration that is lower than the first. This gradient in local impurity concentrations allows the termination structure to effectively manage the positive charge at the interface while reducing the overall area required compared to a uniform wide JTE structure.
Solution Approach 2:
The patent employs parameter changes by systematically varying the impurity concentration across different regions of the JTE structure. The impurity concentration is changed from the first concentration in the first JTE region to the lower second concentration in the second JTE region. This parameter variation enables the structure to maintain breakdown voltage stability while minimizing the termination area, thus resolving the contradiction between reliability and chip size.
2Reliability
If a wide JTE structure is employed to suppress breakdown voltage variation, then the breakdown voltage stability is improved, but the manufacturing cost increases
Solution Approach 1:
The patent applies local quality by creating a JTE structure with spatially varying impurity concentrations. Specifically, it forms a first JTE region with a first impurity concentration and a second JTE region with a second impurity concentration that is lower than the first. This gradient in local impurity concentrations allows the termination structure to effectively manage the positive charge at the interface while reducing the overall area required compared to a uniform wide JTE structure, thereby reducing manufacturing cost.
Solution Approach 2:
The patent employs parameter changes by systematically varying the impurity concentration across different regions of the JTE structure. The impurity concentration is changed from the first concentration in the first JTE region to the lower second concentration in the second JTE region. This parameter variation enables the structure to maintain breakdown voltage stability while minimizing the termination area, thus resolving the contradiction between reliability and manufacturing cost.
3Area of stationary object
If the termination structure area is reduced for downsizing, then the chip size is reduced, but the breakdown voltage variation increases due to positive charge effects
Solution Approach 1:
The patent applies local quality by creating a JTE structure with spatially varying impurity concentrations. Specifically, it forms a first JTE region with a first impurity concentration and a second JTE region with a second impurity concentration that is lower than the first. This gradient in local impurity concentrations allows the termination structure to effectively manage the positive charge at the interface while reducing the overall area required compared to a uniform wide JTE structure.
Solution Approach 2:
The patent employs parameter changes by systematically varying the impurity concentration across different regions of the JTE structure. The impurity concentration is changed from the first concentration in the first JTE region to the lower second concentration in the second JTE region. This parameter variation enables the structure to maintain breakdown voltage stability while minimizing the termination area, thus resolving the contradiction between area reduction and breakdown voltage stability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The approach effectively reduces the area of the termination structure, allowing for smaller chip sizes and lower costs, while maintaining stable breakdown voltage even with varying positive charge levels at the interface, thus enabling cost-effective downsizing of power conversion devices and three-phase motor systems.
Implementation Method 1
avoid avalanche breakdown
Implementation Method 2
ion-implanting p-type impurities with specific concentrations
Data Source
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Figure 5
AI summary
In a semiconductor device having a silicon carbide device, a technique capable of suppressing variation in a breakdown voltage and achieving reduction in an area of a termination structure is provided. In order to solve the above-described problem, in the present invention, in a semiconductor device having a silicon carbide device, a p-type first region and a p-type second region provided to be closer to an outer peripheral side than the first region are provided in a junction termination portion, a first concentration gradient is provided in the first region, and a second concentration gradient larger than the first concentration gradient is provided in the second region.