SiC JTE Termination Layout for Stable Breakdown Voltage
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Solution Overview
Problem
The design of edge termination structures for SiC semiconductor devices is challenging due to low dopant diffusion coefficients, high interface trap levels, and breakdown voltage instabilities, which affect the device's blocking voltage and reliability.
Innovation Solution
A semiconductor device with a termination area that includes a Junction Termination Extension (JTE) layer and a plurality of laterally spaced apart regions, where the first part of the regions penetrates the JTE layer, and the second part does not, enhancing stability and robustness against surface charges.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If P+ floating guard rings are implemented by implanting P-type impurities, then termination structures can be formed, but high crystal damage and breakdown voltage instabilities occur
Solution Approach 1:
The patent replaces the mechanical implantation process with an epitaxial growth process. Instead of implanting P-type impurities (mechanical/physical process), the invention uses in-situ doped epitaxial layers to form the termination structures. This substitution eliminates the high crystal damage associated with high-dose implantation while achieving the desired electrical characteristics for voltage blocking.
Solution Approach 2:
The invention changes the doping method from post-growth implantation to in-situ doping during epitaxial growth. This parameter change allows for better control of dopant distribution and concentration profiles, achieving the required electrical properties without the damaging effects of high-dose implantation.
2Reliability
If high dose implants are used for P dopant activation, then floating rings can be formed, but poor activation and high crystal damage occur
Solution Approach 1:
The patent incorporates dopants during the epitaxial growth process itself, performing the doping action preliminarily before device fabrication is complete. This in-situ doping during growth ensures proper dopant activation and distribution without requiring subsequent high-dose implantation steps, thereby achieving reliable electrical properties while simplifying the overall manufacturing process.
3Reliability
If standard Si termination architectures are used, then termination can be implemented, but efficiency is reduced due to high interface traps in SiC/passivation interface
Solution Approach 1:
The patent applies different doping concentrations and structures at different locations within the termination region. By creating a graded structure with varying P-type doping levels in the epitaxial layers, the invention locally optimizes the electrical properties to compensate for interface trap effects, thereby improving overall termination efficiency without requiring complete redesign of the standard architecture.
Data Source
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AI summary
A semiconductor device, comprising a semiconductor body comprising a semiconductor substrate and an epitaxial layer formed on the semiconductor substrate, said epitaxial layer being of the first conductivity type, and wherein an active area and a termination area adjacent the active area are arranged in the epitaxial layer, wherein the termination area comprises a Junction Termination Extension, JTE, layer of the second conductivity type formed in the epitaxial layer extending laterally from the active area thereby forming a JTE region, a plurality of laterally spaced apart regions, said regions being of the second conductivity type and being higher doped than said JTE layer, wherein a first part of said plurality of laterally spaced apart regions are formed within said JTE region such that said first part of said plurality of laterally spaced apart regions penetrate said JTE layer, and a second part of said plurality of laterally spaced apart regions are formed outside said JTE region such that said second part of said plurality of laterally spaced apart regions do not penetrate said JTE layer.