SiC JTE Layer Stabilization via n-type Buffer
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Solution Overview
Problem
The JTE layer in semiconductor devices using SiC substrates is susceptible to variations in fixed charges at the interface with protective films, leading to unstable dielectric breakdown voltage due to varying formation conditions.
Innovation Solution
A semiconductor device with a SiC region and a JTE layer having p-type conductivity, where the JTE layer is formed with a lower impurity concentration than the impurity layer, and a region with n-type conductivity is created on the JTE layer, allowing for a stable dielectric strength by forming an nMOS capacitor structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If a JTE layer is formed in a SiC substrate with a protective film formed over it, then the pn junction can be covered and electric field strength can be reduced, but the dielectric breakdown voltage becomes unstable due to variations in fixed charges at the interface
Solution Approach 1:
An n-type SiC layer is introduced as an intermediary between the p-type JTE layer and the protective film. This intermediate layer acts as a buffer that isolates the JTE layer from fixed charges at the protective film interface, preventing charge accumulation that would otherwise destabilize the dielectric breakdown voltage while still allowing the protective film to cover and reduce electric field strength at the pn junction.
Solution Approach 2:
The patent applies different doping types to different regions: the pn junction area is covered by the protective film for field strength reduction, while the JTE layer area is covered by an n-type SiC layer with opposite conductivity type. This local differentiation in material properties (conductivity type) addresses the specific need to protect against fixed charges at the JTE interface while maintaining the protective film's function at the pn junction.
2Ease of manufacture
If different conditions are used for forming the protective film, then the formation process can be optimized, but the amount of fixed charges at the JTE interface varies greatly, causing dielectric breakdown voltage to vary
Solution Approach 1:
The n-type SiC layer serves as a buffer layer that decouples the JTE layer from variations in protective film formation conditions. Even when protective film formation conditions vary and cause changes in fixed charge amounts at the interface, the n-type layer absorbs these variations and prevents them from directly affecting the JTE layer, thereby maintaining consistent dielectric breakdown voltage across different manufacturing batches.
Solution Approach 2:
The n-type SiC layer is formed beforehand as a cushioning layer that anticipates and absorbs potential variations in fixed charge accumulation. This pre-formed buffer layer provides a stable foundation that compensates for future variations in protective film formation, ensuring that dielectric breakdown voltage remains stable even when manufacturing conditions fluctuate.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration stabilizes the dielectric breakdown voltage by minimizing the impact of fixed charge density variations, ensuring consistent performance regardless of protective film formation conditions.
Implementation Method 1
The JTE layer of Non-Patent Document 1 is susceptible to charges etc. (especially, fixed charges) around the interface between the JTE layer and a protective film formed over the JTE layer.
Data Source
AI summary
In a semiconductor device using a SiC substrate, a Junction Termination Edge (JTE) layer is hardly affected by fixed charge so that a stable dielectric strength is obtained. A semiconductor device according to a first aspect of the present invention includes a SiC epi-layer having n type conductivity, an impurity region in a surface of the SiC epi-layer and having p type conductivity, and JTE layers adjacent to the impurity region, having p type conductivity, and having a lower impurity concentration than the impurity region. The JTE layers are spaced by a distance from an upper surface of the SiC epi-layer, and SiC regions having n type conductivity are present on the JTE layers.