SiC Semiconductor JTE Structure for Withstanding Voltage
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Solution Overview
Problem
Silicon carbide semiconductor devices face significant deterioration in withstanding voltage due to anisotropy in breakdown electric field intensity, leading to a trade-off between voltage and ON-resistance, which is not effectively addressed by existing technologies without increasing costs.
Innovation Solution
A semiconductor device structure is developed using a silicon carbide substrate with specific conductivity type layers and impurity concentrations, including a first semiconductor area as a junction termination extension, a second semiconductor area with a mesh-shaped impurity concentration, and a third semiconductor area, optimized to prevent voltage deterioration by controlling impurity concentration and electrode placement.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single JTE structure is used in silicon carbide semiconductor devices, then manufacturing is simpler and costs are lower, but the withstanding voltage deteriorates significantly due to anisotropy in breakdown electric field intensity
Solution Approach 1:
The JTE structure is divided into three distinct semiconductor areas (first, second, and third) with different impurity concentrations and geometries. The first JTE area has a specific impurity concentration, the second JTE area has a lower impurity concentration, and the third JTE area provides additional termination. This segmentation allows each area to address specific electric field distribution requirements, collectively achieving high withstanding voltage while managing the complexity through a systematic multi-area approach.
Solution Approach 2:
Different semiconductor areas are assigned different impurity concentrations tailored to their specific locations and electric field requirements. The first JTE area uses a higher impurity concentration to handle regions with higher electric field stress, while the second JTE area uses a lower concentration in regions where the electric field is less intense. This local optimization of impurity concentration ensures that each region contributes maximally to the overall withstanding voltage.
2Reliability
If the dose amount of ions is increased to compensate for anisotropy, then withstanding voltage can be maintained, but manufacturing costs and process complexity increase
Solution Approach 1:
Instead of uniformly increasing the ion dose throughout the device, the invention changes the impurity concentration parameter locally across different semiconductor areas. The first JTE area maintains a specific impurity concentration, while the second JTE area uses a lower concentration. This parameter variation approach achieves the necessary withstanding voltage through optimized spatial distribution of impurities rather than brute-force dose increase, thereby controlling manufacturing complexity and cost.
3Reliability
If a complex multi-area JTE structure is implemented, then withstanding voltage is improved, but manufacturing precision requirements increase
Solution Approach 1:
The JTE is segmented into three areas with clearly defined impurity concentration ranges. The first semiconductor area uses impurity concentrations between 1×10^16 to 1×10^18 atoms/cm³, the second area uses 1×10^15 to 1×10^17 atoms/cm³, and the third area provides additional termination. These segmented zones with specified concentration ranges make the manufacturing process more controllable by breaking down the precision requirement into manageable segments rather than requiring uniform high precision across the entire device.
Solution Approach 2:
The invention specifies concrete impurity concentration ranges for each semiconductor area, transforming the abstract requirement of 'high withstanding voltage' into quantifiable manufacturing parameters. By defining specific concentration intervals (e.g., 1×10^16 to 1×10^18 atoms/cm³ for the first area), the patent provides clear manufacturing targets that guide ion implantation processes, making precision control more achievable and measurable.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed structure effectively prevents voltage deterioration while maintaining low manufacturing costs, optimizing withstanding voltage and ON-resistance, and allowing for the formation of Schottky barrier diodes, MISFETs, and IGBTs with improved performance.
Implementation Method 1
since silicon carbide has anisotropy in the breakdown electric field intensity, the electric field at the end of the JTE is deviated at a tilt with respect the C-axis direction where the breakdown electric field intensity is largest
Implementation Method 2
forming a p− type layer (so-called, resurf layer) as the JTE in a manner of continuously, outwardly extending from part of the Schottky electrode to deplete the p− type layer during a reverse bias and reduce the electric field at the end of the Schottky electrode
Data Source
AI summary
A semiconductor device includes: a semiconductor substrate; a first conductivity type semiconductor layer that is formed on the substrate and is made of silicon carbide; an active area formed on a surface of the semiconductor layer; a first semiconductor area of a second conductivity type formed on the surface of the semiconductor layer to surround the active area; a second semiconductor area, provided to adjoin an outer side of the first semiconductor area on the surface of the semiconductor layer and surround the first semiconductor area, in which a second conductivity type impurity area having the same impurity concentration and the same depth as those of the first semiconductor area is formed in a mesh shape; a first electrode provided on the active area; and a second electrode provided on the rear surface of the semiconductor substrate.