SiC Junction Structure on Insulating Substrate for High Breakdown Voltage
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Solution Overview
Problem
Existing SiC semiconductor devices face challenges in achieving high withstand voltage characteristics due to large leakage currents and the need for expensive epitaxial layer formation processes.
Innovation Solution
A SiC semiconductor device is fabricated using an insulating or semi-insulating SiC substrate, with a P/N junction surface formed by a first auxiliary region of a first conductivity type and a second auxiliary region of a second conductivity type, which enables charge compensation and improves breakdown voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a P-epilayer is formed on an N-substrate using ion implantation, then the device structure is simplified, but the leakage current to the substrate becomes large
Solution Approach 1:
The device is segmented into multiple vertical regions (N-drift region, P-base region, N2-buffer region) with distinct functions. The N2-buffer region acts as a separate layer to block leakage current to the substrate, while the P-base region provides charge compensation. This segmentation allows the device to achieve both structural simplicity and low leakage current.
Solution Approach 2:
The N2-buffer region serves as an intermediary layer between the P-base region and the N-substrate. It mediates the electrical interaction by blocking leakage current paths while allowing the charge compensation effect to function, thus resolving the contradiction between structural simplicity and leakage current control.
2Reliability
If an additional buffer layer or sapphire substrate is used to solve depletion effect, then the breakdown voltage is improved, but a new process must be introduced
Solution Approach 1:
The N2-buffer region and P-base region are merged into a single ion implantation process step, where both regions are formed simultaneously by implanting dopants at different depths. This combining approach achieves the breakdown voltage improvement of a buffer layer without requiring a separate epitaxial growth process, thus maintaining ease of manufacture.
Solution Approach 2:
The invention changes the doping parameters (dopant type, concentration, and implantation depth) to create the N2-buffer region with specific electrical characteristics that provide breakdown voltage enhancement. By adjusting these parameters, the desired reliability is achieved while using the existing ion implantation process.
3Object-affected harmful factors
If a super-junction layer with high concentration doping is used, then the on-resistance is lowered, but the breakdown voltage is rapidly reduced due to depletion effect
Solution Approach 1:
The invention converts the harmful depletion effect into a beneficial charge compensation mechanism. By introducing the P-base region with appropriate doping concentration, the depletion regions of the P-base and N-drift regions compensate for each other, extending the depletion layer toward the drain and increasing breakdown voltage while maintaining low on-resistance through high concentration doping in the N-drift region.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution enhances the on-resistance characteristics and significantly improves the breakdown voltage of the SiC semiconductor device, while also simplifying the manufacturing process by eliminating the need for an epitaxial layer.
Implementation Method 1
the P-pillar creates a mutual charge compensation effect with the N-pillar, and serves to help a depletion layer expand from a P-base to the drain
Implementation Method 2
forming a required area by ion implantation
Data Source
AI summary
A SiC semiconductor device having high pressure resistance properties is disclosed. The present invention provides a SiC semiconductor device comprising: a SiC substrate having a first surface and a second surface; an insulating area formed on the second surface side inside the SiC substrate; and a plurality of semiconductor areas including a source area, a base area, and a drain area formed along the first surface on the insulating area, wherein the SiC semiconductor device has a P/N junction parallel to the first surface, the P/N junction extending from the base area toward the drain area on the insulating area and being formed by a first auxiliary region of a first conductive type which is the same conductive type as the source area and a second auxiliary region of a second conductive type which is opposed to the first conductive type.