SiC Laminate Epitaxy for Coherent Polytype Interfaces
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Solution Overview
Problem
Semiconductor devices using SiC laminates with stacked layers of different polytypes face challenges due to the lack of coherent interfaces between heterotypes, leading to carrier scattering and trapping, which degrades device performance and reliability.
Innovation Solution
A SiC laminate is developed with a coherent heterointerface between hexagonal SiC and 3C-SiC layers, where the 3C-SiC layer is grown epitaxially parallel to the close-packed planes of the hexagonal SiC layer, ensuring a lattice-matched interface without twin boundaries, and the inclined planes are arranged to promote supersaturation and prevent incoherent interfaces.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a SiC laminate with stacked layers of different polytypes is used, then the breakdown voltage and on-resistance performance is improved, but carrier scattering and trapping occurs at incoherent interfaces, degrading device reliability
Solution Approach 1:
The invention changes the crystallographic orientation parameter by growing the 3C-SiC layer parallel to the close-packed planes (0001) of the hexagonal SiC layer, creating a lattice-matched coherent interface. This parameter change eliminates the incoherent interface that causes carrier scattering and trapping, thereby improving device reliability while maintaining the performance benefits of polytype stacking.
Solution Approach 2:
The invention creates a composite SiC laminate structure combining hexagonal SiC and 3C-SiC layers with a coherent interface. The hexagonal SiC provides high breakdown voltage due to its wide band gap, while the 3C-SiC layer reduces on-resistance. The coherent interface between these different polytypes eliminates harmful carrier scattering, enabling the composite structure to achieve both high reliability and excellent electrical performance.
2Productivity
If 3C-SiC is grown on hexagonal SiC with tilted substrate surface, then epitaxial growth rate is improved, but incoherent interfaces and stacking faults are generated
Solution Approach 1:
Instead of tilting the substrate surface to promote epitaxial growth (conventional approach), the invention inverts the approach by keeping the substrate surface parallel to the close-packed planes (0001) and achieving high growth rate through other means. This inversion prevents the formation of incoherent interfaces and stacking faults while maintaining high productivity.
3Reliability
If device structure innovations such as recombination promoting layers are added, then on-resistance reduction is achieved, but manufacturing cost increases and yield decreases
Solution Approach 1:
The invention extracts the need for complex recombination promoting layers by directly growing a 3C-SiC layer with low interface state density on the hexagonal SiC substrate. This extraction simplifies the device structure by removing unnecessary intermediate layers while achieving the same on-resistance reduction effect, thereby lowering manufacturing cost and improving yield.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the simultaneous epitaxial growth of SiC layers of different polytypes, reducing manufacturing costs and enhancing the flexibility and performance of semiconductor devices by preventing carrier scattering and trapping, resulting in improved channel mobility and reduced on-resistance.
Implementation Method 1
a single crystal 3C-SiC layer (2) which is overlaid on the single crystal hexagonal SiC layer (1) in a lattice-matched manner, in which a coherent heterointerface (3) is formed between the single crystal 3C-SiC layer (2) and the single crystal hexagonal SiC layer (1)
Implementation Method 2
the inclined planes are arranged to promote supersaturation and prevent incoherent interfaces
Data Source
AI summary
According to one embodiment, a method of producing a SiC laminate having a hexagonal SiC layer and a 3C-SiC layer comprises: forming a seed plane parallel to a close-packed plane of the crystal lattice on the surface of the hexagonal SiC layer; providing an inclined plane, which is inclined with respect to the seed plane, to all faces adjacent to the seed plane; forming a two-dimensional nucleus of 3C-SiC on the seed plane; and epitaxially growing both the two-dimensional nucleus of 3C-SiC and the SiC layers exposed on the inclined plane simultaneously in a direction parallel to the close-packed plane of the crystal lattice.