SiC Semiconductor Layer Structure for Dislocation-Stable Conduction
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Solution Overview
Problem
Semiconductor devices using silicon carbide substrates face challenges in maintaining stable characteristics due to basal plane dislocation expansion into single shockley stacking faults, which affects carrier transport and increases conduction loss.
Innovation Solution
A semiconductor device structure is implemented with multiple semiconductor layers of varying impurity concentrations and point defect densities, including a second semiconductor layer with high point defect density to prevent basal plane dislocation expansion by promoting recombination of minority carriers and forming a recombination center, thereby stabilizing the device operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a silicon carbide substrate is used to maintain stable device characteristics, then reliability is improved, but basal plane dislocation expansion into single Shockley stacking faults occurs, causing conduction loss
Solution Approach 1:
A second semiconductor layer is introduced as an intermediary between the first and third semiconductor layers. This intermediate layer has higher point defect density and lower impurity concentration, serving as a buffer to prevent dislocation expansion while maintaining carrier transport efficiency, thus resolving the contradiction between reliability and conduction loss
Solution Approach 2:
The patent applies local quality by creating a semiconductor layer with specific local characteristics (higher point defect density, lower impurity concentration) at the critical interface region where dislocation expansion occurs, rather than uniformly treating the entire structure. This localized modification prevents dislocation propagation while maintaining overall device performance
2Loss of energy
If impurity concentration is increased to improve carrier transport, then electrical conductivity is improved, but point defect density increases, promoting dislocation expansion
Solution Approach 1:
The patent changes the parameters of the second semiconductor layer by setting its impurity concentration to be lower than the first layer and its point defect density to be higher, creating a specific parameter combination that prevents dislocation expansion while maintaining acceptable carrier transport properties
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed structure effectively prevents basal plane dislocation expansion into single shockley stacking faults, reducing conduction loss and maintaining stable device performance by promoting recombination and controlling impurity concentrations.
Implementation Method 1
a second semiconductor layer of the first conductivity type, the second semiconductor layer being provided on the first semiconductor layer and containing silicon carbide; A point defect density in the second semiconductor layer is the same as or higher than a point defect density in the first semiconductor layer
Data Source
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AI summary
The embodiment is a semiconductor device containing silicon carbide. The semiconductor device (1) includes a semiconductor substrate (10), a first semiconductor portion (20), a second semiconductor portion (30), a third semiconductor portion (40), and a fourth semiconductor portion (50). Each of the first semiconductor portion to the third semiconductor portion contains impurities having a first conductivity type, and the fourth semiconductor portion contains impurities having a second conductivity type. A carrier concentration of the second semiconductor portion is the same as or lower than a carrier concentration of the first semiconductor portion. The carrier concentration of the second semiconductor portion is the same as or higher than a carrier concentration of the third semiconductor portion. A point defect density of the second semiconductor portion is the same as or higher than a point defect density of the first semiconductor portion, and is higher than a point defect density of the third semiconductor portion.