SiC Layer Coupling for Vertical Power Delivery in Chip Packages
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Solution Overview
Problem
Current semiconductor packages face challenges in providing high electrical power to a large number of components within chips and packages, particularly in high-bandwidth computing applications, due to limitations in voltage range and efficiency of power distribution.
Innovation Solution
The integration of a silicon carbide (SiC) layer coupled with a gallium nitride (GaN) layer and a silicon (Si) layer using fusion bonding, hybrid bonding, layer transfer, and bump and island formation techniques, allowing for efficient voltage stepping down from high voltages to lower voltages for effective power distribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If high voltage power distribution is used to provide more power to components, then power delivery capability is improved, but electrical losses and heat generation increase
Solution Approach 1:
The patent segments the power distribution function across multiple layers (SiC layer, intermediate layer, GaN layer) with different voltage levels. High voltage power is delivered through the SiC layer, stepped down in the intermediate layer, and distributed at lower voltages through the GaN layer, dividing the power distribution task into manageable segments that reduce overall electrical losses
Solution Approach 2:
The patent transitions from planar power distribution to three-dimensional vertical power distribution across stacked layers. By utilizing the vertical dimension with multiple bonding interfaces and layered structures, the system achieves efficient power delivery and voltage transformation that reduces current path lengths and minimizes resistive losses
2Productivity
If more layers are integrated to enable voltage stepping, then power distribution efficiency is improved, but manufacturing complexity increases
Solution Approach 1:
The bonding interfaces between layers are designed to be self-aligning and self-bonding through direct physical contact and bonding processes. The layers automatically establish proper electrical and mechanical connections without requiring complex external alignment mechanisms or additional fastening components, reducing manufacturing complexity
Solution Approach 2:
The patent combines multiple functions into integrated layered structures where the intermediate layer simultaneously provides electrical connection, mechanical support, and voltage transformation. The bonding interfaces merge electrical interconnection and structural bonding into unified interfaces, reducing the number of separate components and assembly steps
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables the provision of significantly more power to semiconductor packages by efficiently stepping down high voltages, reducing IR losses, and improving signal integrity, thereby supporting high-density transistors and memory in computing devices.
Implementation Method 1
The integration of a silicon carbide (SiC) layer coupled with a gallium nitride (GaN) layer and a silicon (Si) layer using fusion bonding
Implementation Method 2
The integration of a silicon carbide (SiC) layer coupled with a gallium nitride (GaN) layer and a silicon (Si) layer using hybrid bonding
Implementation Method 3
allowing for efficient voltage stepping down from high voltages to lower voltages for effective power distribution
Data Source
AI summary
Embodiments described herein may be related to apparatuses, processes, systems, and/or techniques for fabricating semiconductor packages that use a SiC layer that is coupled with another layer that includes another material. The SiC layer may be an active layer that includes devices, such as transistors, that are coupled with devices that may be in the other layer. The SiC layer may be coupled with the other layer using fusion bonding, hybrid bonding, layer transfer, and/or bump and island formation techniques. Other embodiments may be described and/or claimed.