Silicon Carbide Layer Transfer for Ohmic Vertical Conduction
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Solution Overview
Problem
The existing methods for transferring a monocrystalline silicon carbide working layer onto a silicon carbide carrier substrate via the SMART CUT process do not achieve the desired low resistivity and ohmic behavior necessary for vertical electrical conduction, especially when high-temperature annealing leads to adverse crystal defects.
Innovation Solution
A process involving implantation of light species to create a buried brittle plane, followed by chemical etching or polishing to remove the damaged surface layer, molecular adhesion bonding, and a heat treatment between 1300° C. and 1700° C. to transfer the working layer, with optional additional layers for improved bonding and chemical-mechanical smoothing to achieve low surface roughness and ohmic behavior.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high-temperature annealing is applied to restore structural and electrical qualities, then electrical properties of the working layer improve, but crystal defects increase and quality deteriorates
Solution Approach 1:
The patent applies heat treatment at optimized temperature parameters (1300-1700°C) and duration to achieve the desired electrical properties while avoiding excessive temperature that would cause crystal defects. This parameter optimization resolves the contradiction between improving electrical properties and preventing defect formation.
Solution Approach 2:
The patent performs preliminary surface preparation including chemical-mechanical polishing and cleaning before bonding to ensure low surface roughness and high bonding quality. This preliminary action prevents the need for aggressive high-temperature annealing later, thereby avoiding crystal defects while still achieving good electrical properties.
2Reliability
If extremely high-temperature annealing is used to achieve low resistivity, then vertical conduction improves, but manufacturing complexity and risk of defects increase
Solution Approach 1:
The patent optimizes the heat treatment parameters (temperature range 1300-1700°C, controlled duration) to achieve the desired vertical conduction performance without requiring extremely high temperatures. This parameter optimization simplifies the manufacturing process while maintaining low resistivity and ohmic behavior at the bonding interface.
3Strength
If the working layer is transferred onto a carrier substrate, then mechanical support is improved, but bonding interface quality and electrical conduction become critical challenges
Solution Approach 1:
The patent performs preliminary surface preparation including chemical-mechanical polishing and cleaning of both the working layer and carrier substrate surfaces before bonding. This ensures low surface roughness and high bonding quality, achieving both mechanical support and excellent electrical conduction at the bonding interface.
Solution Approach 2:
The patent optimizes bonding parameters including temperature, pressure, and atmosphere conditions to achieve high-quality molecular adhesion at the bonding interface. These controlled parameters ensure both mechanical strength and electrical conduction requirements are met simultaneously.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The process results in a semiconductor structure with excellent electrical properties and improved vertical conduction performance, achieving ohmic behavior without the need for extremely high-temperature annealing, which minimizes crystal defects and enhances the quality of the working layer and bonding interface.
Implementation Method 1
implanting light species in the donor substrate on a front face, in order to form a damage profile, which can notably be measured by means of Rutherford backscattering spectrometry, the profile having a main peak of depth defects defining a buried brittle plane and a secondary peak of defects defining a damaged surface layer
Implementation Method 2
removing the damaged surface layer by means of chemical etching and/or by means of chemical-mechanical polishing of the front face of the donor substrate
Implementation Method 3
joining the donor substrate, on the side of the front surface, and the carrier substrate by means of molecular adhesion, in order to form an assembly bonded along a bonding interface
Implementation Method 4
a heat treatment between 1300° C. and 1700° C. to transfer the working layer
Implementation Method 5
chemical-mechanical smoothing to achieve low surface roughness
Data Source
AI summary
A method for producing a semiconductor structure comprises: a) provision of a monocrystalline silicon carbide donor substrate and a silicon carbide support substrate; b) production of a useful layer to be transferred, comprising—implanting light species in the donor substrate at a front face, so as to form a damage profile, the profile having a main peak of deep-level defects defining a buried brittle plane and a secondary peak of defects defining a damaged surface layer, and—removing the damaged surface layer by chemical etching and/or chemical mechanical polishing of the front face of the donor substrate, so as to form a new front surface of the donor substrate; c) assembly of donor substrate with the support substrate; and d) separation along the buried fragile plane, leading to the transfer of the useful layer onto the support substrate, so as to form the semiconductor structure.