SiC Semiconductor Mesa Heterojunction Leakage Control
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Solution Overview
Problem
Current semiconductor devices, particularly those using silicon carbide, face challenges in optimizing forward current and leakage current due to limitations in doping profiles and heterojunction design, which affect their performance in high-voltage applications.
Innovation Solution
The semiconductor device incorporates a silicon carbide layer with a mesa structure and doped regions formed in trenches and over the mesa, featuring varying dopant profiles and conductivity types to create heterojunctions, which are optimized through specific implantation processes and layer formations to enhance current handling and reduce leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional doping profiles and heterojunction design are used in silicon carbide semiconductor devices, then manufacturing simplicity is maintained, but forward current performance and leakage current control are suboptimal
Solution Approach 1:
The patent applies local quality by creating distinct doped regions with different doping concentrations and types at specific locations within the silicon carbide layer. The first doped region has a first doping concentration, the second doped region has a second doping concentration, and the third doped region has a third doping concentration, with each region tailored to optimize local electrical characteristics for reducing leakage current and improving forward current performance.
Solution Approach 2:
The patent employs composite materials by forming a heterojunction between the silicon carbide layer and a different semiconductor material layer. This heterojunction structure combines materials with different band gaps and electrical properties to achieve superior current handling characteristics and leakage reduction compared to homogeneous silicon carbide structures.
2Reliability
If heterojunctions are formed at interfaces between different materials with different band gaps, then current handling capability is enhanced, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies preliminary action by forming the first and second doped regions within trenches that are etched into the silicon carbide layer before forming the heterojunction. This preliminary trench formation and doping establishes precise spatial boundaries and material compositions that facilitate subsequent heterojunction formation with controlled interfaces, reducing manufacturing precision challenges.
Solution Approach 2:
The patent segments the silicon carbide layer into distinct regions including trenches containing doped semiconductor material and mesa regions with different doped regions. This segmentation creates well-defined interfaces and separate functional zones that simplify heterojunction formation and improve interface definition precision during manufacturing.
3Reliability
If multiple doped regions with varying dopant concentrations are formed, then leakage current is reduced and knee voltage is lowered, but device structure complexity increases
Solution Approach 1:
The patent applies local quality by assigning specific doping concentrations to specific regions: the first doped region in the first trench has a first doping concentration, the second doped region in the second trench has a second doping concentration, and the third doped region over the mesa has a third doping concentration. Each region's doping profile is locally optimized to contribute to overall leakage reduction and knee voltage optimization while maintaining manageable device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design improves the performance of silicon carbide semiconductor devices by tailoring dopant profiles, resulting in reduced leakage current and lower knee voltage, enabling high reverse voltage capabilities with low forward resistance.
Implementation Method 1
a heterojunction defined at an interface between the third doped region and the mesa
Implementation Method 2
a first doped region layer adjacent a first side of the mesa, a second doped region adjacent a second side of the mesa, a third doped region over the mesa
Data Source
AI summary
A semiconductor device and a method of manufacturing a semiconductor are provided. In an embodiment, a first trench is formed in a silicon carbide layer. A second trench is formed in the silicon carbide layer to define a mesa in the silicon carbide layer between the first trench and the second trench. A first doped semiconductor material is formed in the first trench and a second doped semiconductor material is formed in the second trench. A third doped semiconductor material is formed over the mesa to define a heterojunction at an interface between the third doped semiconductor material and the mesa.