SiC Mesa Trench Layout With Sidewall Wiring for Reliable Connectivity
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Solution Overview
Problem
Existing SiC semiconductor devices lack an efficient and reliable wiring structure that facilitates optimal electrical connectivity and performance.
Innovation Solution
A SiC semiconductor device with a mesa structure and sidewall wiring configuration, featuring a trench gate and trench source structure, where sidewall wiring covers the connecting surface and is electrically connected to the trench structures, enhancing electrical connectivity and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional wiring structures are used in SiC semiconductor devices, then manufacturing processes are simpler, but electrical connectivity and reliability between trench gate and source structures are insufficient
Solution Approach 1:
The patent transitions from planar wiring to three-dimensional sidewall wiring that utilizes the vertical dimension. The sidewall wiring is formed on the sidewalls of the mesa structure, extending from the first surface through the connecting surface to the second surface, thereby achieving robust electrical connectivity between trench gate and source structures by exploiting the third dimension (vertical height) rather than relying solely on horizontal routing.
Solution Approach 2:
The sidewall wiring is nested within the mesa structure, with the wiring embedded in the sidewalls of the hollowed region. This nesting approach allows the wiring to be integrated within the existing device geometry, achieving reliable electrical connections without adding significant external complexity to the overall device structure.
2Area of stationary object
If trench gate and source structures are integrated closely, then device area is reduced, but electrical connectivity and signal integrity deteriorate
Solution Approach 1:
By moving the wiring connection path to the vertical sidewalls of the mesa structure, the patent enables close integration of trench gate and source structures on the first surface while maintaining electrical connectivity through the vertical dimension. The sidewall wiring travels along the connecting surface, providing a short and reliable connection path that does not require increased horizontal spacing between structures.
Data Source
AI summary
A SiC semiconductor device includes a SiC chip having a main surface that includes a first surface, a second surface hollowed in a thickness direction outside the first surface, and a connecting surface connecting the first surface and the second surface, and in which a mesa is defined by the first surface, the second surface and the connecting surface, a trench structure formed at the first surface such as to be exposed from the connecting surface, and a sidewall wiring that is formed on the second surface such as to cover the connecting surface and that is electrically connected to the trench structure.