SiC Trenched MISFET Field Relaxation Layer Design
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Solution Overview
Problem
Trenched MISFETs face challenges in relaxing the OFF-time electric field on the gate insulating film while maintaining sufficient voltage resistance and minimizing ON resistance, with existing solutions involving high processing costs and reliability issues due to epitaxial defects and channel punch-through.
Innovation Solution
A silicon carbide semiconductor device structure featuring a resistance relaxation layer and a field relaxation layer, where the field relaxation layer is wider than the resistance relaxation layer, is used to relax the OFF-time electric field and reduce ON resistance, thereby enhancing voltage resistance and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a p-type layer is disposed immediately below the gate insulating film at the lower portion of the trench, then the electric field applied during OFF time to the gate insulating film is relaxed and voltage resistance is maintained, but ON resistance increases due to inhibition of carrier flow from channel to drain electrode
Solution Approach 1:
The patent applies local quality by creating different doping regions with specific spatial characteristics. The p-type layer is formed with a first concentration region directly below the gate insulating film (for field relaxation) and a second concentration region laterally extended from the first region (for reduced ON resistance). This spatial differentiation of doping concentrations allows the structure to simultaneously relax the electric field at the gate interface while providing low-resistance paths for carrier flow in the ON state.
Solution Approach 2:
The p-type layer is segmented into two distinct concentration regions: a first concentration region positioned directly below the gate insulating film to relax the electric field, and a second concentration region that laterally extends from the first region to reduce ON resistance. This segmentation allows each region to fulfill its specific function independently while working together to resolve the contradiction between gate insulating film reliability and ON resistance.
2Reliability
If existing epitaxial techniques are used to form p-type layers, then field relaxation is achieved, but processing costs increase and reliability decreases due to epitaxial defects
Solution Approach 1:
The patent replaces the epitaxial growth process with ion implantation technology. Instead of using complex epitaxial techniques that require precise temperature control and result in defects, the invention uses ion implantation to form the p-type layers with specified concentrations and distributions. This substitution simplifies the manufacturing process, reduces costs, and improves reliability by avoiding epitaxial defects while achieving the same field relaxation effect.
Data Source
AI summary
Disclosed herein is a technique for realizing a high-performance and high-reliability silicon carbide semiconductor device. A trenched MISFET with a trench formed into the drift through a p-type body layer 105 includes an n-type resistance relaxation layer 109 covering the bottom portion of the trench, and a p-type field relaxation layer 108. The p-type field relaxation layer 108 is separated from the trench bottom portion via the resistance relaxation layer 109, and is wider than the resistance relaxation layer 109. This achieves a low ON resistance, high reliability, and high voltage resistance at the same time. By forming the field relaxation layer beneath the trench, feedback capacitance can be controlled to achieve a high switching rate and high reliability.