3D SiC MISFET Cell Structure for Short-Circuit Thermal Reliability
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Solution Overview
Problem
SiC MOSFETs face limitations in fault handling and reliability due to higher power density leading to faster thermal transients and reduced short-circuit endurance, along with a trade-off between conduction losses and short-circuit withstand time, compared to their Si counterparts.
Innovation Solution
A power semiconductor device with a 3D SiC MISFET structure featuring a drift layer, well region, and doped regions of specific shapes and doping concentrations, which includes discontinuous parts to limit current path resistance and improve junction temperature management, thereby enhancing reliability and trade-off between conduction losses and short-circuit withstand time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If SiC MOSFETs use higher power density design, then efficiency and maximum junction temperature are improved, but thermal transient speed increases and reliability deteriorates
Solution Approach 1:
The source region is divided into multiple discrete source regions arranged in a grid pattern, with each source region having associated first and second doped regions. This segmentation distributes the current paths throughout the device, reducing peak current density and improving thermal management, thereby maintaining reliability while preserving efficiency benefits.
Solution Approach 2:
Different doped regions are created with specific doping concentrations and types (n-type and p-type) in different locations. The first doped regions have different properties than the second doped regions, allowing optimization of local electrical and thermal characteristics to balance efficiency and reliability.
2Volume of moving object
If cell pitch is reduced to decrease die size, then power density increases, but short-circuit endurance time decreases
Solution Approach 1:
The device structure is segmented into multiple discrete source regions and doped regions arranged in a grid pattern. This segmentation creates distributed current paths that reduce peak current density during short-circuit events, thereby extending short-circuit endurance time even when overall die size is reduced through compact grid arrangement.
Solution Approach 2:
The invention transitions from planar current paths to a three-dimensional doped region structure with multiple layers and discrete regions. This dimensional change creates more complex current paths that distribute stress and heat more effectively, improving short-circuit withstand capability in compact die designs.
3Loss of energy
If conduction losses are reduced through device optimization, then efficiency improves, but short-circuit withstand time is reduced
Solution Approach 1:
Multiple discrete source regions with associated doped regions create distributed current paths that reduce peak current density. This segmentation allows lower conduction losses through improved current distribution while simultaneously reducing thermal stress during short-circuit events, maintaining or improving withstand time despite efficiency optimizations.
Solution Approach 2:
Specific doping concentrations and types are used in different regions to optimize electrical characteristics. By carefully controlling doping parameters in first and second doped regions, the device achieves low conduction losses while maintaining robust short-circuit protection through localized electrical property optimization.
Data Source
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AI summary
A power semiconductor device (1) is specified, comprising - a drift layer (2) of a first conductivity type, - a well region (3) of a second conductivity type being different from the first conductivity type, and - a first doped region (4) of the first conductivity type and a second doped region (5) of the second conductivity type, wherein - the well region (3), the first doped region (4) and the second doped region (5) are provided at a first side of the power semiconductor device (1), - the first doped region (4) and the second doped region (5) are spaced apart (6) from the drift layer (2) by the well region (3), and - the second doped region (5) is completely surrounded by the first doped region (4) in lateral directions, and - the second doped region (5) comprises at least two parts (6), which are spaced apart (6) from one another in lateral directions by the first doped region (4). Furthermore, a method for producing a power semiconductor device (1) is specified.