SiC Power MISFET Trench Structure for Gate Reliability
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Solution Overview
Problem
Silicon carbide semiconductor devices with trench structures face issues of dielectric breakdown in the gate insulating film and energization deterioration due to Basal Plane Dislocations, leading to reduced reliability and performance.
Innovation Solution
A silicon carbide power MISFET design with a trench structure where the gate electrode is embedded in a p-type body layer, and a metal layer forms a Schottky junction on the n-type current diffusion layer, preventing the bottom of the trench from extending to the n-type drift layer, thus moderating the electric field on the gate insulating film and preventing energization deterioration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the trench bottom extends to the n-type drift layer to reduce channel resistance, then carrier mobility is improved, but the gate insulating film withstanding voltage decreases and dielectric breakdown occurs
Solution Approach 1:
The patent applies local quality by creating different structural configurations in different regions of the device. Specifically, some trenches extend to the drift layer to provide low-resistance current paths, while other trenches are terminated before reaching the drift layer to maintain high gate insulating film strength. This spatial differentiation allows simultaneous optimization of both carrier mobility and dielectric reliability.
Solution Approach 2:
The patent segments the trench structure into multiple types: first trenches that extend to the drift layer for low resistance, and second trenches that are terminated in the body layer for high gate insulation strength. This segmentation allows the device to achieve both low on-resistance and high gate withstanding voltage by distributing different functional trenches throughout the device structure.
2Device complexity
If current flows through the PN junction to reduce device complexity, then the structure is simplified, but Basal Plane Dislocations expand and cause energization deterioration
Solution Approach 1:
The patent introduces an intermediary Schottky barrier diode structure formed by a metal layer contacting the n-type drift layer. This Schottky diode acts as an alternative current path that bypasses the PN junction, preventing BPD expansion while maintaining relatively simple device structure. The Schottky barrier serves as a mediator that redirects current flow away from the harmful PN junction region.
Solution Approach 2:
The patent converts the potentially harmful effect of current flow through BPD-containing regions into a beneficial outcome by designing Schottky barrier diodes that intentionally channel current through controlled metal-semiconductor junctions. This transforms what would be a degradation mechanism into a protective feature that prevents BPD expansion while maintaining device functionality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances the voltage withstandability of the gate insulating film, reduces on-resistance, and prevents energization deterioration, thereby improving the reliability and performance of the silicon carbide semiconductor device.
Implementation Method 1
a metal layer that forms a Schottky junction on an upper face of the n-type current diffusion layer neighboring with the trench
Implementation Method 2
the gate insulating film electric field in an off state is decreased... the withstanding voltage of the gate insulating film decreases
Data Source
AI summary
A silicon carbide semiconductor device includes an n-type silicon carbide semiconductor substrate, a drain electrode electrically connected to a rear face, an n-type semiconductor layer having a second impurity concentration lower than the first impurity concentration, a p-type first semiconductor region, an n-type second semiconductor region, and an n-type third semiconductor region. A trench is formed having a gate electrode therein in which the bottom face of the trench contacts the p-type semiconductor region. A metal layer is electrically connected to the third semiconductor region, and a source electrode electrically connects the second semiconductor region and the metal layer to each other.