SiC Semiconductor Module Asymmetric Current Path Design
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Solution Overview
Problem
Existing semiconductor modules with parallel-connected main and body diodes suffer from inrush currents that deteriorate SiC crystals in the semiconductor substrate due to parasitic inductance effects, which previous solutions have not adequately addressed.
Innovation Solution
The semiconductor module design includes a first semiconductor chip with a SiC field effect transistor and a second semiconductor chip with a diode, where the current paths for inrush currents are engineered to have different lengths, resulting in varying parasitic inductances that suppress the inrush current flowing through the body diode, thereby reducing SiC crystal deterioration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the main diode and body diode are connected in parallel with equal current path lengths, then the circuit structure is simple and easy to manufacture, but inrush current flows through the body diode causing SiC crystal deterioration
Solution Approach 1:
The patent applies asymmetry by intentionally making the current path lengths asymmetric. The current path through the main diode is designed to be shorter than the current path through the body diode, creating different parasitic inductance values. This asymmetric design causes inrush current to preferentially flow through the main diode with lower inductance, protecting the SiC crystals in the body diode from deterioration while maintaining manufacturing feasibility.
2Object-affected harmful factors
If the current path length difference is increased to suppress inrush current, then SiC crystal deterioration is reduced, but the device complexity increases
Solution Approach 1:
The patent applies local quality by modifying only specific portions of the current paths rather than redesigning the entire device. The lead frame structure is locally adjusted to create different path lengths - for example, by extending the lead frame trace length for the body diode path or positioning connection points differently. This localized modification achieves the desired inductance difference without requiring complete device redesign, thus limiting the increase in device complexity.
3Stability of the object's composition
If parasitic inductance is increased in the body diode path to suppress inrush current, then SiC crystal integrity is maintained, but the inductance increase may affect circuit performance
Solution Approach 1:
The patent applies partial action by increasing parasitic inductance only in the body diode path just enough to suppress inrush current, rather than excessively increasing it. The current path length difference is designed to create a moderate inductance difference that is sufficient to redirect inrush current away from the body diode, while not so large as to significantly impact normal circuit operation. This balanced approach protects SiC crystal integrity while minimizing negative effects on circuit performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively reduces the inrush current through the body diode, minimizing SiC crystal deterioration and maintaining the integrity of the semiconductor substrate, thus preventing an increase in on-resistance of the MOSFET.
Implementation Method 1
Since the first current path is longer than the second current path, a parasitic inductance of the first current path is larger than a parasitic inductance of the second current path. In the first current path having the larger parasitic inductance, an increase in the current is suppressed as compared to that in the second current path having the smaller parasitic inductance.
Data Source
AI summary
A semiconductor module may include: a first semiconductor chip including a first semiconductor substrate including a field effect transistor and constituted of SiC, a drain electrode and a source electrode provided on the first semiconductor substrate; a second semiconductor chip including a second semiconductor substrate including a diode, a cathode electrode and an anode electrode provided on the second semiconductor substrate; a first lead frame including a first main terminal and connected to the drain electrode and the cathode electrode; and a second lead frame including a second main terminal and connected to the source electrode and the anode electrode. A first current path extending from the second to first main terminal via the first semiconductor chip may be longer than a second current path extending from the second to first main terminal via the second semiconductor chip.