SiC Semiconductor Module Insulating Layer Thickness Optimization
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Solution Overview
Problem
Semiconductor modules face thermal fatigue and reduced heat dissipation due to the large difference in linear expansion coefficients between semiconductor chips, insulating substrates, and heat sinks, leading to cracks in solder joints and a shorter service life, especially when using harder materials like SiC and thin insulating layers.
Innovation Solution
A semiconductor module design with an insulating substrate having a thicker insulating layer (2.66 to 5 times the thickness of the semiconductor chip) and specific metal joining members to manage stress and strain, allowing for controlled cracking in the second metal joining member without compromising heat dissipation for the semiconductor chips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If the insulating layer is made thinner to improve heat dissipation, then heat dissipation performance is improved, but thermal fatigue and stress strain increase leading to shorter service life
Solution Approach 1:
The patent optimizes the thickness parameter of the insulating layer to a specific range (2.66 to 5 times the semiconductor chip thickness) that balances heat dissipation performance with stress reduction. This parameter optimization resolves the contradiction by finding the optimal value that satisfies both thermal management and mechanical reliability requirements.
2Strength
If the semiconductor chip is made thinner to reduce stress strain on the first solder, then stress strain is reduced, but mass production efficiency decreases due to heavy wearing of polishing tools
Solution Approach 1:
The patent introduces the insulating layer as an intermediary element between the semiconductor chip and the heat sink. This intermediary structure absorbs and distributes stress, reducing the stress strain on the first solder joint without requiring the semiconductor chip itself to be thinner, thereby maintaining mass production efficiency.
3Volume of moving object
If semiconductor chips are densely arranged to achieve downsizing, then package size is reduced, but heat dissipation area decreases compromising thermal management
Solution Approach 1:
The patent extends the heat dissipation path from a two-dimensional surface problem to a three-dimensional structure by utilizing the vertical dimension through the optimized insulating layer thickness. This allows for dense chip arrangement while maintaining effective heat dissipation through the thickness dimension rather than requiring larger surface area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Ensures high heat dissipation for semiconductor chips by minimizing cracks in the first metal joining members and tolerating larger cracks in the second metal joining member, thereby extending the service life and maintaining efficient heat transfer.
Implementation Method 1
the difference among the semiconductor chips, the insulating substrate, and the heat sink in a linear expansion coefficient causes thermal fatigue in the first solder and the second solder
Implementation Method 2
The semiconductor chip and the insulating substrate are joined together with first solder. The insulating substrate and the heat sink are joined together with second solder
Data Source
AI summary
A semiconductor module includes an insulating substrate including an insulating layer, a first metal pattern formed on an upper surface of the insulating layer, and a second metal pattern formed on a lower surface of the insulating layer, a semiconductor chip that is formed of SiC and is fixed to the first metal pattern with a first metal joining member, and a heat sink that is fixed to the second metal pattern with a second metal joining member, wherein the semiconductor chip has a thickness that is equal to or larger than 0.25 mm and equal to or smaller than 0.35 mm, and the insulating layer has a thickness that is larger than the thickness of the semiconductor chip by a factor of 2.66 inclusive to 5 inclusive.