SiC Module Packaging Layout for High-Current Thermal Balance
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Solution Overview
Problem
Current commercial kiloampere-level single-switch SiC power semiconductor modules face issues such as large size, low power density, poor static/dynamic parallel current-sharing performance, and inadequate thermal dissipation, making them unsuitable for high-speed switching applications.
Innovation Solution
A packaging structure for kiloampere-level single-switch SiC power semiconductor modules, featuring multiple parallel-connected SiC chips on distributed DBC substrates, optimized copper regions, and a PinFin direct liquid-cooled baseplate, with symmetrical chip layout and reverse bonding to decouple drive and power loops, and encapsulation for protection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple SiC chips are connected in parallel to increase current capacity, then the current rating increases, but the module size increases and power density decreases
Solution Approach 1:
The patent transitions from planar chip arrangement to a three-dimensional stacked configuration using multiple DBC substrates arranged in layers. This vertical stacking enables multiple chips to occupy the same footprint area by utilizing the Z-dimension, thereby increasing current capacity without proportionally increasing module volume and maintaining high power density.
Solution Approach 2:
The patent implements a nested structure where multiple DBC substrates with SiC chips are stacked and integrated within a compact module housing. The substrates are arranged in a nested configuration with optimized spacing, allowing maximum chip density within the available volume while maintaining thermal and electrical performance.
2Quantity of substance
If multiple SiC chips are connected in parallel to increase current capacity, then the current rating increases, but the thermal dissipation performance deteriorates
Solution Approach 1:
The patent divides the thermal management system into multiple independent heat dissipation paths by using separate DBC substrates for each chip. Each substrate has its own thermal vias and cooling contacts, allowing heat from multiple chips to be dissipated simultaneously through parallel thermal pathways, preventing thermal accumulation and maintaining effective thermal dissipation at high current capacities.
Solution Approach 2:
The DBC substrates serve as intermediary thermal management components between the SiC chips and the cooling system. These substrates incorporate optimized thermal via structures that efficiently conduct heat away from the chips, acting as thermal intermediaries that improve overall heat dissipation performance while supporting high current capacity operation.
3Quantity of substance
If multiple SiC chips are connected in parallel to increase current capacity, then the current rating increases, but the static/dynamic parallel current-sharing performance deteriorates
Solution Approach 1:
The patent employs asymmetric bonding wire configurations and optimized copper region layouts on each DBC substrate to compensate for inherent variations between parallel chips. By introducing controlled asymmetries in the interconnection structures, the design balances the overall current distribution across all parallel chips, improving static and dynamic current-sharing performance while maintaining high current capacity.
4Ease of manufacture
If commercial Si IGBT module packaging structures are used for SiC chips, then the structure is available, but the performance is inadequate for high-speed switching SiC chips
Solution Approach 1:
The patent modifies key packaging parameters including reducing parasitic inductance through optimized bond wire configurations, minimizing loop areas, and using low-inductance interconnection structures. These parameter changes in the packaging design are specifically tailored to match the high-speed switching characteristics of SiC chips, enabling reliable operation at frequencies where traditional Si IGBT packaging would fail.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The structure achieves a smaller size, higher power density, improved static/dynamic current-sharing, and enhanced thermal performance, significantly increasing current capacity and reliability for high-power applications.
Implementation Method 1
a baseplate, fixedly connected to the above power DBC substrates and the signal DBC substrate, for effectively conducting heat generated by the SiC chips
Data Source
AI summary
The present invention discloses a packaging structure for a kiloampere-level single-switch SiC power semiconductor module, primarily including components such as SiC chips, substrates, baseplate, power and signal terminals, integrated gate/Kelvin source resistors, and housing. The packaging structure proposed in this invention improves the electrothermal performance of multi-chip SiC power modules, reduces the size of the power module, and breaks through the limitations on the number of parallel-connected SiC chips. It significantly enhances the current capacity and power density of existing SiC power semiconductor modules, making it particularly suitable for 1.7 kV˜6.5 kV single-switch power semiconductor modules in high-power applications such as rail transit traction and flexible DC power transmission. Furthermore, the packaging structure proposed in this invention is compatible with conventional fabrication processes such as soldering, wire bonding, and potting encapsulation. The fabrication method is mature and suitable for large-scale engineering applications.