Self-Aligned SiC MOS Channel Layout for Gate-Safe Fabrication
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Solution Overview
Problem
The challenge in manufacturing Metal Oxide Semiconductor (MOS) devices, particularly Silicon Carbide (SiC) MOS devices, lies in the ultra-high-temperature processing requirements which differ from silicon technology, making it difficult to transfer self-aligned gate processes and double diffusion processes, as polysilicon gates cannot survive implantation annealing and ion diffusion is limited in SiC.
Innovation Solution
A double hard-mask fabrication process is used to separate the source region into independent parts for low-ohmic access and channel definition, allowing for self-aligned channel formation without significant changes to the design, enabling the use of standard tools and processes in industrial environments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If self-aligned gate process is applied to SiC devices, then manufacturing precision is improved, but device reliability deteriorates because polysilicon gate cannot survive implantation annealing at ultra-high temperatures
Solution Approach 1:
The patent extracts the gate electrode formation step from the self-aligned process sequence, performing it before the ultra-high-temperature implantation annealing. This separates the gate electrode creation from the thermal processing that would otherwise destroy polysilicon gates, allowing self-aligned channel formation to proceed without compromising gate integrity.
Solution Approach 2:
The gate electrode is formed in advance, before the implantation annealing step, so that it is already in place and protected when the ultra-high-temperature processing occurs. This preliminary action ensures the gate survives the thermal process while still enabling subsequent self-aligned channel definition.
2Manufacturing precision
If double diffusion process is applied to SiC MOS devices, then manufacturing precision is improved, but device complexity increases due to limited ion diffusion in SiC even at elevated temperatures
Solution Approach 1:
The patent replaces the traditional double diffusion process with a direct ion implantation method. Instead of relying on thermal diffusion mechanisms that are limited in SiC, the invention uses mechanical ion implantation to achieve precise doping profiles, thereby maintaining manufacturing precision while reducing process complexity.
3Area of stationary object
If standard photolithography is used for cell integration, then device area is reduced, but manufacturing precision deteriorates due to resolution and overlay accuracy limitations
Solution Approach 1:
The patent employs self-aligned processes where previously formed structures serve as their own alignment references for subsequent steps. The gate electrode and implanted regions automatically define the positioning for next processing steps, eliminating the need for high-precision photolithography overlay while maintaining small cell dimensions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for reliable manufacturing of SiC MOS devices with improved manufacturability and process reliability, enabling smaller elementary cell pitch, higher integration density, and lower device resistance, while maintaining the benefits of SiC technology such as wide-bandgap and high thermal conductivity.
Implementation Method 1
The lightly doped source is implanted within the self-aligned channel process after creation of a spacer
Implementation Method 2
SiC microfabrication requires ultra-high-temperature processing for implantation annealing, e.g., at about 1700° C.
Implementation Method 3
thermal oxidation, e.g., at about 1300° C.
Implementation Method 4
contact annealing, e.g., at about 1000° C.
Data Source
AI summary
A Metal-Oxide-Semiconductor (MOS) device is provided. The MOS device comprises: a control electrode; a current output electrode of a first semiconductor doping type or of a second semiconductor doping type; a buffer layer of the first semiconductor doping type and a drift layer of the first semiconductor doping type; a body region of the second semiconductor doping type, embedded in the drift layer, the body region configured to form a Junction Field Effect Transistor (JFET) region in the drift layer; a current input electrode comprising a first region and a second region of the first semiconductor doping type embedded in the body region, wherein a channel of the MOS device is configured to be formed between a junction of the second region of the current input electrode to the body region and a junction of the body region to the JFET region.