SiC MOS Gate Edge Termination for Breakdown Voltage
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Solution Overview
Problem
Current power semiconductor devices face limitations in achieving both high current and high speed, with silicon-based devices reaching material constraints, and existing edge termination structures in semiconductor devices often lead to reduced breakdown voltage due to electric field concentration and process variations.
Innovation Solution
A semiconductor device with an edge termination structure outside the active region, featuring multiple p-type regions of varying impurity concentrations, including a double zone junction termination extension (JTE) structure, which mitigates electric field concentration and extends the outermost p+-type base region into a flat portion to prevent depletion layer expansion, thereby enhancing breakdown voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional edge termination structures are used, then manufacturing is simpler, but breakdown voltage decreases due to electric field concentration
Solution Approach 1:
The edge termination structure is segmented into multiple zones with different impurity concentrations (first p-type region with concentration 1×10^16 to 1×10^18 atoms/cm³, second p-type region with concentration 1×10^14 to 1×10^16 atoms/cm³). This segmentation distributes the electric field across multiple regions, preventing concentration at any single point and thereby maintaining high breakdown voltage while managing structural complexity through systematic zonation.
Solution Approach 2:
Different regions of the edge termination structure are assigned different impurity concentrations tailored to their specific functional requirements. The first p-type region closer to the active area has higher impurity concentration to handle higher electric fields, while the second p-type region farther away has lower concentration for optimal field distribution. This local optimization of material properties prevents electric field concentration and enhances breakdown voltage without requiring uniform complexity throughout the structure.
2Productivity
If silicon-based devices are used, then manufacturing is well-established, but current density and switching speed are limited by material constraints
Solution Approach 1:
The patent changes the fundamental material parameter from silicon to wide bandgap semiconductor (GaN or SiC), which enables operation at higher current densities and switching speeds beyond silicon's theoretical limits. This parameter change in bandgap energy allows the device to achieve productivity improvements while the multi-zone edge termination structure adapts to the new material's electrical characteristics, demonstrating both parameter transformation and structural adaptability.
Data Source
AI summary
A MOS gate structure is provided on a p-type base layer side of a silicon carbide semiconductor base formed by sequentially forming on a front surface of an n+-type silicon carbide substrate, an n-type drift layer and a p-type base layer by epitaxial growth. On the base front surface, in an edge termination structure region, a step portion occurring between the p-type base layer and the n-type drift layer, and a flat portion farther outward than the step portion are provided. In a surface layer of the n-type drift layer, a p+-type base region constituting the MOS gate structure is provided so as to contact the p-type base layer. The outermost p+-type base region extends from an active region into the flat portion and the entire lower side of this portion is covered by an innermost p−-type region constituting an edge termination structure provided in the flat portion.