Planar SiC MOS Layout With Metal-Filled Gap to Prevent Passivation Cracks
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Solution Overview
Problem
The planar silicon carbide MOS device experiences cracking issues due to weak points at the interface between the PI layer and the PA layer on the side wall of the etched through hole, affecting device reliability, and the source and gate pads are dispersedly distributed.
Innovation Solution
A planar silicon carbide MOS device with a gap between the gate and source metal layers, where the gap is filled with a metal covering layer instead of a PI layer, reducing stress on the passivation layer and enhancing the cell region's effective area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a PI layer is used to fill the etched through hole in existing planar silicon carbide MOS devices, then the through hole can be filled and covered, but the PA layer is prone to cracking at the interface between the PI layer and PA layer, affecting device reliability
Solution Approach 1:
The patent removes the PI layer from the etched through hole filling, extracting the problematic element that caused cracking. Instead of using PI layer to fill the through hole, the patent uses a different approach where the through hole is filled with a metal layer (Al or Cu) that is compatible with the PA layer, thereby eliminating the interface cracking issue between PI and PA layers.
Solution Approach 2:
The patent changes the material parameter of the filling layer from PI (polyimide) to metal (Al or Cu). This material substitution fundamentally changes the interface properties between the filling layer and PA layer, eliminating the cracking problem. The metal material has better mechanical compatibility and adhesion characteristics with the PA layer compared to PI material.
2Reliability
If source metal layer and gate metal layer are distributed dispersedly to achieve electrical connection, then electrical functionality is achieved, but the source pad and gate pad are distributed dispersedly, increasing device complexity
Solution Approach 1:
The patent merges the source pad and gate pad into a single integrated pad structure. By designing the metal layers and contacts such that both source and gate connections are achieved through a unified pad region, the patent reduces the number of separate pad elements from multiple dispersed pads to a single consolidated pad, thereby simplifying the device structure while maintaining electrical functionality.
Data Source
AI summary
The present invention provides a planar silicon carbide MOS device and a preparation method therefor. In the planar silicon carbide MOS device, a gap on an inner side of a passivation layer is filled with a metal covering layer instead of a polyimide (PI) layer at the gap. The structure increases an effective area of a cell region, and further avoids the PI layer from applying a large stress to the passivation layer at the gap, that is, reduces a stress on the passivation layer on a side wall of the gap, which protects the passivation layer, and alleviates cracking of the passivation layer on the side wall of the gap, thereby optimizing reliability of the planar silicon carbide MOS device.