SiC MOS Thyristor Base Region Doping for Low ON Resistance
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Solution Overview
Problem
Current silicon carbide (SiC) power semiconductor devices face limitations in high-speed and high-current applications due to low channel mobility and reliability issues with gate insulating films, particularly in ultra-high voltage applications beyond 10 kV, where ON resistance remains high and minority carrier storage is inefficient.
Innovation Solution
The silicon carbide semiconductor device incorporates a MOS thyristor structure with p-type base regions of varying impurity concentrations, connected by MOS structures, which enhance minority carrier storage and reduce ON resistance by modulating conductivity, preventing punch-through and improving electron injection, thereby reducing power loss.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional SiC power semiconductor devices are used, then high voltage and high-temperature characteristics are achieved, but ON resistance remains high and power loss increases
Solution Approach 1:
The patent applies parameter changes by varying the impurity concentration distribution in the base region, specifically creating a non-uniform doping profile with higher impurity concentration near the collector and lower concentration toward the emitter. This gradient in impurity concentration optimizes the balance between reducing ON resistance and maintaining breakdown voltage, thereby reducing power loss while preserving reliability
Solution Approach 2:
The patent implements local quality by creating regions with different impurity concentrations within the base region. The base region is divided into zones with varying doping levels, where each zone has optimized local properties: higher impurity concentration regions provide lower resistance paths, while lower impurity concentration regions maintain adequate breakdown characteristics, collectively reducing overall power loss
2Stability of the object's composition
If gate insulating films are used in SiC devices, then device stability is improved, but reliability issues occur in ultra-high voltage applications
Solution Approach 1:
The patent addresses gate insulating film reliability by changing the electrical parameters of the base region, specifically optimizing the impurity concentration profile to reduce electric field stress on the gate insulating film. By creating a more gradual potential gradient through controlled doping variations, the maximum electric field intensity at the gate insulating film interface is reduced, preventing breakdown and enhancing reliability in ultra-high voltage applications while preserving device stability
3Speed
If conventional SiC devices are used, then high voltage characteristics are achieved, but high-speed operation is limited
Solution Approach 1:
The patent improves switching speed by changing the impurity concentration parameters in the base region. The optimized doping profile reduces the base transit time by creating a more favorable carrier gradient, allowing faster minority carrier extraction. Simultaneously, the parameter optimization ensures that channel mobility is maintained by avoiding excessive impurity concentrations that would cause scattering, thus achieving high-speed operation with preserved reliability
4Loss of energy
If impurity concentration is increased to reduce ON resistance, then power loss decreases, but minority carrier storage efficiency is reduced
Solution Approach 1:
The patent resolves this contradiction by applying local quality through spatially varying impurity concentration. Regions closer to the collector junction have higher impurity concentration to reduce ON resistance and power loss, while regions toward the emitter have lower impurity concentration to maintain adequate minority carrier storage capacity. This non-uniform distribution allows each region to optimize its local function, collectively achieving both low power loss and sufficient carrier storage
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed device achieves lower ON resistance and reduced power loss, enabling efficient high-speed operation in ultra-high voltage applications by optimizing p-type base region configurations and minority carrier management.
Implementation Method 1
a MOS thyristor structure with p-type base regions of varying impurity concentrations, connected by MOS structures
Implementation Method 2
enhance minority carrier storage and reduce ON resistance by modulating conductivity
Implementation Method 3
reduce ON resistance by modulating conductivity, preventing punch-through
Implementation Method 4
improving electron injection, thereby reducing power loss
Data Source
AI summary
A silicon carbide semiconductor device includes first semiconductor areas and second semiconductor areas. The first semiconductor areas have a first semiconductor layer of a second conductivity type, a second semiconductor layer of a first conductivity type, first semiconductor regions of the second conductivity type, second semiconductor regions of the first conductivity type, gate electrodes, and first electrodes. The second semiconductor areas have the first semiconductor layer, the second semiconductor layer, third semiconductor regions of the second conductivity type, the gate electrodes, and the first electrodes. The first semiconductor regions include low- impurity-concentration regions and high-impurity-concentration regions. The third semiconductor regions have a potential equal to that of the first electrodes. The first semiconductor regions are connected to the third semiconductor regions by MOS structures. In the first semiconductor regions, the high-impurity-concentration regions are provided at positions different from positions facing the first electrodes.