SiC MOSFET Gate Insulation and Annealing Process
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Solution Overview
Problem
The manufacturing process of silicon carbide (SiC) semiconductor devices requires higher processing temperatures for annealing, which poses challenges in achieving efficient impurity activation and device performance, especially in high-temperature operations.
Innovation Solution
A semiconductor device and manufacturing method involving a MOSFET structure with specific layer configurations and ion implantation processes using high melting point masks, followed by annealing and insulating film formation to achieve precise layer alignment and reduced gate-source capacitance, enabling efficient impurity activation and improved switching characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If higher processing temperature annealing is used for SiC semiconductor devices, then impurity activation is improved, but manufacturing complexity and difficulty increase
Solution Approach 1:
The patent segments the annealing process into multiple stages with different temperature profiles. The first annealing step is performed at a lower temperature (1500-1700°C) to activate impurities, followed by a second annealing step at a higher temperature (1700-1900°C) to repair crystal damage. This segmentation allows impurity activation to be achieved while managing the overall manufacturing complexity by breaking down the high-temperature requirement into controlled stages.
Solution Approach 2:
The patent applies preliminary protective actions before the high-temperature annealing process. A protective film is formed on the semiconductor device before annealing to prevent contamination and damage during the high-temperature processing. Additionally, the first annealing step is performed before the second annealing step to preliminarily activate impurities, reducing the burden on the subsequent high-temperature step.
2Reliability
If higher processing temperature annealing is used for SiC semiconductor devices, then device performance in high temperature operation is improved, but processing complexity increases
Solution Approach 1:
The patent merges multiple functions into the annealing process. The annealing steps simultaneously achieve impurity activation, crystal damage repair, and electrical characteristic optimization. The protective film formation is merged with the annealing process, serving both as a protective barrier and as part of the overall thermal processing sequence, thereby reducing the number of separate processing steps.
Solution Approach 2:
The patent utilizes parameter changes in the annealing process to achieve multiple objectives. By varying the temperature, time, and atmosphere parameters between the first and second annealing steps, the process optimizes both impurity activation and crystal repair. The first annealing uses parameters optimized for impurity activation, while the second uses parameters optimized for crystal repair, thereby managing processing complexity through parameter optimization.
3Manufacturing precision
If precise layer alignment is achieved through ion implantation with high melting point masks, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The patent introduces high melting point masks as intermediary elements during the ion implantation process. These masks serve as mediators to define precise implantation regions and protect areas that should not be implanted. The masks are formed using standard photolithography and deposition techniques, and their high melting point property allows them to withstand subsequent high-temperature annealing processes without deforming, thereby maintaining manufacturing precision while using relatively simple processing steps.
4Productivity
If gate-source capacitance is reduced through specific insulating film formation, then switching characteristics are improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies local quality by forming insulating films with different properties in different regions. The gate insulating film is formed with specific thickness and material properties to optimize capacitance characteristics in the gate region. The source and drain insulating films are formed with different properties to optimize their respective functions. This localized optimization improves switching characteristics while managing manufacturing precision requirements through region-specific processing.
Solution Approach 2:
The patent performs preliminary formation of the gate insulating film before ion implantation and subsequent processing steps. This preliminary action establishes the base capacitance characteristics early in the process, allowing subsequent steps to focus on other critical dimensions. The gate insulating film is formed with controlled thickness and uniformity to preliminarily set the capacitance level, reducing the burden on subsequent manufacturing steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method allows for the production of SiC semiconductor devices with enhanced switching characteristics and compatibility with miniaturization, while maintaining stable performance and high accuracy in device fabrication.
Implementation Method 1
activating the first ions and the second ions by heat treatment
Implementation Method 2
forming a third semiconductor region of the first conductivity type by implanting second ions into the second semiconductor region through the first mask and the second mask
Data Source
AI summary
According to one embodiment, a semiconductor device includes a first semiconductor region, a second semiconductor region, a third semiconductor region, a first electrode, a first insulating section, and a second insulating section. The first semiconductor region includes silicon carbide, is of a first conductivity type and includes first and second parts. The second semiconductor region includes silicon carbide, is of a second conductivity type and is provided on the second part. The third semiconductor region includes silicon carbide, is of the first conductivity type and is provided on the second semiconductor region. The first electrode is provided on the first part and the third semiconductor region. The first insulating section is provided on the third semiconductor region and juxtaposed with the first electrode. The second insulating section is provided between the first electrode and the first part and between the first electrode and the first insulating section.