SiC MOSFET Arsenic Doping Reduces Leak Current
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Solution Overview
Problem
Silicon carbide (SiC) semiconductor devices face challenges in reducing leak current due to defects like threading screw dislocations, as existing methods fail to effectively control impurity diffusion and concentration, leading to increased on-resistance and power loss.
Innovation Solution
The implementation of an n-type silicon carbide region with arsenic impurity concentration varying from 1.0×10^18 cm^-3 to 5.0×10^20 cm^-3, formed by epitaxial growth and ion implantation, is used to create a vertical MOSFET or trench IGBT structure, where arsenic is strategically distributed to reduce leak current by minimizing diffusion into dislocations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If ion implantation is used to control impurity concentration in SiC, then carrier concentration can be controlled, but impurity diffusion into dislocations increases leading to higher leak current
Solution Approach 1:
The patent changes the chemical parameter of the impurity from conventional nitrogen/phosphorus to arsenic. Arsenic has different diffusion characteristics in SiC that reduce its tendency to diffuse into threading screw dislocations, thereby maintaining precise impurity concentration control while reducing leak current.
Solution Approach 2:
The patent applies a doping profile configuration successfully used in Si-based power devices to SiC devices. By copying the effective impurity distribution pattern from Si technology, the patent achieves similar performance benefits in SiC, reducing both on-resistance and leak current through optimized carrier concentration distribution.
2Ease of manufacture
If thermal diffusion is used for impurity control, then the process is simple and widely applicable, but it is difficult to apply to SiC due to very small diffusion coefficient
Solution Approach 1:
The patent replaces thermal diffusion (thermal field-based process) with ion implantation (mechanical/physical process). Ion implantation delivers impurities directly to the desired depth through controlled ion bombardment, bypassing the limitation of SiC's extremely low thermal diffusion coefficient while maintaining process reliability.
3Loss of energy
If high impurity concentration is used to reduce on-resistance, then power loss in steady state decreases, but leak current increases due to defect-related conduction
Solution Approach 1:
The patent creates different impurity concentration zones within the drift region. By locally optimizing the arsenic concentration profile, the patent achieves high carrier concentration where needed for low on-resistance while maintaining lower concentrations near dislocation-prone areas, thus reducing both power loss and leak current simultaneously.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces leak current density and maintains device performance even with high threading screw dislocation densities, enhancing the reliability and efficiency of SiC semiconductor devices.
Implementation Method 1
ion implantation is usually used for SiC. As the ion species to be implanted, nitrogen (N) or phosphorus (P) is used for an n-type impurity
Implementation Method 2
the p-type silicon carbide region is formed by an epitaxial growth method
Data Source
AI summary
A silicon carbide semiconductor device includes plural p-type silicon carbide epitaxial layers provided on an n+-type silicon carbide substrate. In some of the p-type silicon carbide epitaxial layers, an n+ source region is provided in at least a region of an upper portion. The n+ source region includes a first portion that contains arsenic and a second portion that contains phosphorous.