SiC MOSFET Module Turn-Off Control for Avalanche Robustness
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
SiC MOSFETs face challenges in avalanche breakdown during unclamped inductive switching due to parasitic transistor operation, leading to reduced avalanche capability and potential failure, especially when multiple chips are connected in parallel, as the turn-off timing of individual chips can vary, causing current concentration and thermal issues.
Innovation Solution
The semiconductor module incorporates a control unit that monitors and adjusts the turn-off time of each SiC chip based on sensed current and hole current, ensuring the parasitic transistor is turned off before it can cause excessive electron current flow, and designs the chip structure to minimize contact resistance and maximize contact area to prevent parasitic transistor operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple SiC chips are connected in parallel to increase current capacity, then the overall power handling capability is improved, but current concentration and turn-off timing variations cause parasitic transistor operation and reduced avalanche capability
Solution Approach 1:
The patent modifies the turn-off timing parameter of each SiC chip based on sensed current and hole current characteristics. By dynamically adjusting the turn-off time parameter, the system ensures that chips with higher current carry less total current, preventing parasitic transistor operation and maintaining avalanche capability even when multiple chips are connected in parallel.
2Loss of energy
If the turn-off time of SiC chips is extended to reduce switching losses, then energy efficiency is improved, but parasitic transistor operation occurs leading to thermal failure
Solution Approach 1:
The patent implements a feedback mechanism where the control unit continuously senses the current and hole current from each SiC chip during operation. Based on this real-time feedback, the control unit dynamically adjusts the turn-off timing to prevent parasitic transistor operation, thereby avoiding thermal failure while maintaining efficient switching performance.
Solution Approach 2:
The patent transitions from fixed turn-off timing to dynamic turn-off timing adjustment. The turn-off time is no longer a static parameter but is continuously adapted based on the actual operating conditions and sensed current characteristics, allowing the system to optimize between switching losses and thermal safety in real-time.
3Reliability
If the chip structure is designed to minimize contact resistance, then conductivity is improved, but manufacturing complexity increases
Solution Approach 1:
The patent segments the contact structure into multiple distinct layers including an aluminum layer, a titanium layer, and a nickel layer. This segmented multi-layer contact structure achieves low contact resistance by optimizing each layer's contribution while maintaining manufacturability through standard thin-film deposition techniques.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the avalanche capability of each SiC chip by ensuring timely turn-off and reducing the likelihood of parasitic transistor operation, thereby preventing thermal failure and increasing the number of chips that can be connected in parallel without risking avalanche breakdown.
Implementation Method 1
avalanche breakdown occurs in an unclamped inductive switching (UIS) test
Implementation Method 2
designs the chip structure to minimize contact resistance and maximize contact area to prevent parasitic transistor operation
Data Source
AI summary
Provided is a semiconductor module including a plurality of SiC chips electrically connected in parallel and each having a MOSFET and a parasitic transistor formed therein, and a control unit which controls switching of the MOSFET in each of the SiC chips, and for all of the plurality of SiC chips, at least in a state where the parasitic transistor is turned on, the control unit controls, to 0.9 μs or less, a turn-off time of the MOSFET corresponding.