SiC MOSFET Chip Layout for Uniform Current and Body Diode Protection
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Solution Overview
Problem
The use of silicon carbide in MOSFETs for high-temperature and high-pressure applications leads to increased ON-resistance due to reflux currents flowing through the pn junction diode, causing stacking defects and reliability degradation.
Innovation Solution
Incorporating Schottky barrier diodes (SBDs) in MOSFETs to redirect reflux currents, and optimizing the arrangement of MOSFETs and bonding wires to minimize current variations, thereby preventing pn junction diode operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a pn junction diode is used as a body diode in silicon carbide MOSFET, then the MOSFET can operate at high temperature and high pressure, but reflux current causes stacking defect growth and increased ON-resistance
Solution Approach 1:
The patent changes the fundamental operating parameter of the body diode from bipolar (pn junction) to unipolar (Schottky barrier). This parameter change eliminates carrier recombination effects that cause stacking defects, thereby reducing ON-resistance while maintaining high-temperature and high-pressure operation capability through the silicon carbide material system.
Solution Approach 2:
The patent replaces the traditional pn junction diode structure with a Schottky barrier diode structure. This structural substitution copies the essential rectification function while eliminating the harmful bipolar carrier recombination mechanism, preventing stacking defect growth and improving device reliability.
2Reliability
If Schottky barrier diode is used instead of pn junction diode, then stacking defect growth is prevented and reliability is improved, but device structure becomes more complex
Solution Approach 1:
The patent extracts and eliminates the bipolar carrier recombination mechanism from the body diode structure by replacing the pn junction with a Schottky barrier diode. This extraction removes the source of stacking defects while maintaining the essential diode function, improving reliability without requiring additional external components or complex control circuits.
3Ease of operation
If MOSFETs are arranged with bonding wires to connect terminals, then electrical connection is achieved, but current variations occur leading to pn junction diode operation
Solution Approach 1:
The patent employs asymmetric arrangement of MOSFETs and bonding wires to minimize current path differences. By carefully designing the layout to balance the electrical paths, the patent reduces current variations that would otherwise cause unwanted pn junction diode operation, thereby improving current stability while maintaining ease of electrical connection.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances the reliability of silicon carbide MOSFETs by reducing current variations and preventing stacking defects, thus improving the overall performance and longevity of the semiconductor device.
Implementation Method 1
Incorporating Schottky barrier diodes (SBDs) in MOSFETs to redirect reflux currents, and optimizing the arrangement of MOSFETs and bonding wires to minimize current variations, thereby preventing pn junction diode operation.
Data Source
AI summary
A semiconductor device includes first, second, and third metal layers on a surface of the insulating substrate. A first terminal is connected to the first metal layer at a first region. A second terminal is connected to the second metal layer at a second region. An output terminal is connected to the third metal layer. First chips are aligned along a first direction on the first metal layer. Second chips are aligned along the first direction on the third metal layer. A first wire connects a first upper electrode of a first chip to the third metal layer. A second wire connects a second upper electrode of a second chip to the second metal layer. The second chips are between the first chips and the third metal layer in a second direction perpendicular to the first direction. Available conductive routes between the first and second terminals are made more uniform.