SiC Superjunction MOSFET Edge Termination for Breakdown Margin

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Solution Overview

Problem

Conventional silicon carbide (SiC) MOSFETs with a superjunction (SJ) structure face issues with breakdown voltage distribution, where the edge termination region has lower breakdown voltage than the active region, leading to increased susceptibility to avalanche breakdown and reduced resistance to destruction.

Innovation Solution

The silicon carbide semiconductor device incorporates a parallel pn layer with varying lengths of p-type column regions in the active and edge termination regions, creating a p-rich upper portion and n-rich lower portion in the active region, and a p-type column region structure in the edge termination region to adjust charge balance and enhance breakdown voltage margin.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of energy

If a superjunction structure with uniform p-type and n-type column regions is used in both active and edge termination regions, then on-resistance is reduced, but breakdown voltage becomes lower in the edge termination region making it more susceptible to avalanche breakdown

Engineering Contradiction:
Improveon-resistanceVSAvoidbreakdown voltage margin
Core Design Contradiction:
Loss of energyVSReliability

Solution Approach 1:

The patent applies local quality by differentiating the SJ structure configuration between the active region and edge termination region. In the active region, uniform p-type and n-type column regions maintain low on-resistance. In the edge termination region, only n-type column regions are provided without corresponding p-type column regions, creating a localized structural difference that raises breakdown voltage where it is most needed while preserving the low on-resistance特性 in the active region.

Inventive Principle:
Principle #3Local quality

2Ease of manufacture

If p-type column regions are provided in the edge termination region with the same configuration as the active region, then manufacturing is simplified, but the edge termination region has lower breakdown voltage and reduced resistance to destruction

Engineering Contradiction:
Improvestructural uniformityVSAvoidresistance to destruction
Core Design Contradiction:
Ease of manufactureVSStrength

Solution Approach 1:

The patent implements local quality by providing n-type column regions in the edge termination region with different characteristics from those in the active region. Specifically, the n-type column regions in the edge termination region have a different width ratio relative to adjacent p-type column regions compared to the active region, creating localized structural optimization that enhances breakdown voltage and resistance to destruction without requiring complete structural uniformity throughout the device.

Inventive Principle:
Principle #3Local quality

3Reliability

If the width of n-type column regions is made larger relative to p-type column regions in the edge termination region, then breakdown voltage is increased, but charge balance is disrupted

Engineering Contradiction:
Improvebreakdown voltageVSAvoidcharge balance
Core Design Contradiction:
ReliabilityVSStability of the object's composition

Solution Approach 1:

The patent applies parameter changes by adjusting the width ratio of n-type to p-type column regions differently in the edge termination region compared to the active region. This parameter modification optimizes the breakdown voltage characteristics in the edge termination region while the overall charge balance is maintained through coordinated design of the SJ structure across both regions, achieving both high breakdown voltage and charge balance stability.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS20230275122A1Silicon carbide semiconductor device
Publication Date: 2023.08.31 FUJI ELECTRIC CO LTD
  • US20230275122A1 patent drawing
  • US20230275122A1 patent drawing
  • US20230275122A1 patent drawing

AI summary

A semiconductor device including a semiconductor substrate, a parallel pn layer and a device structure provided in the semiconductor substrate, first and second electrodes respectively provided at two main surfaces of the semiconductor substrate, the first electrode being electrically connected to the device structure. The parallel pn layer includes first-conductivity-type column regions and second-conductivity-type column regions that are adjacently disposed and repeatedly alternate with one another in a first direction parallel to the first main surface, that each extend in a second direction parallel to the first main surface and orthogonal to the first direction, and that are of a same impurity concentration. A portion of the second-conductivity-type column regions is shorter than the rest thereof. The parallel pn layer has a first portion and a second portion respectively closer to the first and second main surfaces, the first portion being more p-rich, and less n-rich, than the second portion.