SiC MOSFET Body Diode Defect Expansion via Buffer Layer
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Solution Overview
Problem
The operation of a body diode in SiC semiconductor elements leads to increased resistance and loss due to bipolar operation, particularly when reflux currents flow through the body diode, causing instability and malfunction.
Innovation Solution
A silicon carbide semiconductor device is designed with a parallel connection structure of SiC-MOSFET and SiC-SBD, where the reflux current is directed through the SiC-SBD instead of the MOSFET body diode, using a drain electrode, ohmic electrode, Schottky electrode, and specific conductivity type regions to prevent defect expansion and reduce ON-resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a body diode is used for reflux current in a SiC-MOSFET, then the device can be simplified and compactified, but bipolar operation causes crystal defect expansion and increased ON-resistance
Solution Approach 1:
An n-type buffer layer is introduced as an intermediary between the p-type well region and the n-type drift region. This buffer layer prevents direct contact between p-type and n-type carriers, eliminating bipolar operation and crystal defect expansion while maintaining the simplicity of using the body diode for reflux current. The buffer layer acts as a mediator that blocks harmful carrier recombination while allowing the desired electrical functionality.
2Reliability
If gate voltage is controlled in a narrow range to allow reflux current through the channel, then body diode operation is avoided, but noise easily opens the channel causing through-current
Solution Approach 1:
The n-type buffer layer serves as a physical intermediary that prevents p-type carriers from reaching the n-type drift region. This structural mediation eliminates the need for precise gate voltage control to prevent bipolar operation, as the buffer layer inherently blocks the harmful carrier interaction regardless of gate voltage fluctuations or noise conditions.
3Ease of operation
If bipolar operation occurs in the SiC semiconductor element, then reflux current can flow through the body diode, but crystal defects expand due to carrier recombination energy
Solution Approach 1:
The n-type buffer layer is positioned between the p-type well region and n-type drift region to act as a barrier that prevents p-type carriers from entering the n-type drift region. This intermediary structure allows reflux current to flow through the body diode while blocking the carrier recombination that causes crystal defect expansion, effectively separating the useful current flow from the harmful bipolar operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively suppresses defect expansion and reduces ON-resistance by routing reflux currents through the SiC-SBD, enhancing the stability and efficiency of the semiconductor device.
Implementation Method 1
a Schottky electrode formed in contact with a second conductivity type second withstand voltage holding region on the drain electrode with the Schottky electrode
Data Source
AI summary
A silicon carbide semiconductor device includes an ohmic electrode and a Schottky electrode that are in contact with the drain electrode respectively on the drain electrode and are next to each other; a first conductivity type first withstand voltage holding region in contact with the ohmic electrode on the ohmic electrode; a second conductivity type second withstand voltage holding region in contact with the Schottky electrode on the Schottky electrode and is next to the first withstand voltage holding region; a second conductivity type well region in contact onto the first and second withstand voltage holding regions; a first conductivity type source region selectively provided on a surface layer of the well region; and a gate electrode opposite to a channel region defined by the well region sandwiched between the source region and the first withstand voltage holding region, with a gate oxide film interposed therebetween.