SiC MOSFET Channel Length Control with Buffer Layer Spacers

The patent introduces a buffer layer as an intermediary between the gate electrode and the semiconductor substrate. This buffer layer serves as a pattern mask during etching processes, enabling self-alignment of channel length without requiring the gate electrode itself to function as the mask. The buffer layer can be deposited and patterned separately, allowing precise control of channel dimensions while avoiding the complexity of using gate electrode as direct mask in ultra-high temperature processes

The buffer layer is deposited and patterned before the gate electrode formation. This preliminary action establishes the channel length definition early in the process sequence, enabling subsequent steps to align to this pre-defined pattern. The buffer layer pattern serves as a template that guides subsequent etching and material deposition, ensuring consistent channel dimensions throughout the device structure

The buffer layer pattern automatically defines the channel length through self-aligned etching processes. The etch process uses the buffer layer as a stop layer, ensuring that the channel length is determined by the buffer layer dimensions rather than by separate masking steps. This self-service mechanism ensures uniform channel length across all devices in the batch, improving reliability without adding significant process complexity

The buffer layer thickness and pattern dimensions provide direct feedback control for channel length. By controlling the buffer layer deposition parameters and pattern dimensions, the channel length is precisely defined. The buffer layer acts as a reference that feedbacks the channel dimensions throughout subsequent processing steps, ensuring consistency and enabling process optimization