SiC Power MOSFET Buried Doping Layout for Lower Ron
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Solution Overview
Problem
Silicon carbide (SiC) power MOSFETs have high channel resistance and low carrier mobility, leading to high specific on resistance (Ron) at voltages less than 3300 volts, which is difficult to reduce without complicating device design or compromising reverse blocking voltage.
Innovation Solution
The semiconductor power device incorporates buried doped regions in the drift layer, connected by a strip of doped regions, which electrically connect well regions and buried doped regions, reducing the voltage drop in the gate insulation layer and allowing for a thinner gate insulation layer, thereby minimizing Ron.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the channel length is reduced to lower specific on resistance (Ron), then Ron decreases, but leakage increases and reverse blocking voltage decreases
Solution Approach 1:
The drift layer is segmented into multiple regions by introducing buried doped regions that divide the drift layer into several sections. This segmentation allows the device to achieve low on-resistance through multiple parallel current paths while maintaining adequate blocking voltage through the distributed structure of the segmented drift regions.
Solution Approach 2:
Different regions of the drift layer are given different doping characteristics through the buried doped regions. The local quality varies across the drift layer, with doped regions providing low resistance paths and undoped regions providing high breakdown voltage, allowing simultaneous optimization of both Ron and reverse blocking voltage.
2Loss of energy
If complicated processing steps including trenches and new technologies are introduced to reduce Ron, then Ron decreases, but device complexity increases
Solution Approach 1:
The buried doped regions are formed by merging the doping process with existing drift layer formation steps. The doped regions are integrated into the drift layer fabrication sequence, combining multiple functions (drift layer formation and resistance reduction) into a unified processing approach that avoids separate trench formation and additional complex steps.
Solution Approach 2:
The buried doped regions are formed using self-aligned processes where the doping automatically occurs in the desired locations based on the drift layer structure itself. This self-service approach eliminates the need for precise alignment steps and complex masking procedures, reducing device complexity while achieving the desired resistance reduction.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration significantly reduces the specific on resistance (Ron) by mitigating voltage drop in the gate insulation layer, allowing for a thinner layer and lower resistance to current flow without affecting reverse blocking voltage, as demonstrated in simulation results with Ron reduced to 0.04Ω.
Implementation Method 1
the presences of the buried doped regions 104, and thus the thickness of the gate insulation layer 108 can be significantly reduced so as to lower the specific on resistance (Ron)
Implementation Method 2
a plurality of buried doped regions 104, a plurality of gates 106, a gate insulation layer 108, a plurality of well regions 110, a plurality of source regions 112, and a plurality of well contact regions 114
Data Source
AI summary
A semiconductor power device includes a substrate, a drift layer disposed on the substrate, buried doped regions, gates, a gate insulation layer, well regions, source regions, and well contact regions. The buried doped regions are in the drift layer and parallel to each other, and each of the buried doped regions is a predetermined distance from an upper surface of the drift layer. The gates are on the drift layer and directly above the buried doped regions. The gate insulation layer is between the drift layer and the gates. The well regions are in the drift layer between the gates and separated from the buried doped regions, wherein the well regions and the buried doped regions are electrically connected. The source regions are within the well regions between the gates, and each of the well contact regions passes through the source region and contacts with the well.