SiC MOSFET Gate Drain Capacitance Reduction
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Solution Overview
Problem
SiC Power MOSFETs face challenges in reducing gate drain capacitance without impacting other performance parameters, such as breakdown voltage and switching speed, due to high doping concentrations and material properties of Silicon Carbide, which lead to increased switching losses and system size limitations.
Innovation Solution
The method involves forming P-type wells in the N-type doped drift layer, depositing a thicker oxide over the drift region, and using counter-doping at the edges of the body regions to reduce gate drain capacitance while maintaining or improving breakdown voltage through controlled implantation and oxide patterning techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high doping concentration is used in the drift region to reduce On resistance, then conductivity is improved, but gate drain capacitance increases
Solution Approach 1:
The patent applies different doping concentrations at different locations: high doping in the drift region for low On resistance, and low doping at the body region edges for reduced gate drain capacitance. This spatial variation in doping quality resolves the contradiction between conductivity and capacitance.
Solution Approach 2:
The patent changes the doping concentration parameter from uniform to non-uniform distribution. By reducing doping concentration specifically at the body region edges while maintaining high doping in the drift region, the patent optimizes both On resistance and gate drain capacitance characteristics.
2Reliability
If high packing density is used to reduce On resistance, then channel resistance decreases, but input and reverse capacitances increase
Solution Approach 1:
The patent implements local quality optimization by concentrating channels in high-density regions for low On resistance while creating low-density regions at body edges to reduce capacitances. The terraced oxide structure enables this spatial differentiation of channel density.
Solution Approach 2:
The patent segments the drift region into areas with different channel densities. The terraced oxide creates distinct regions: high-density channel regions under the gate and low-density regions at the body edges, allowing independent optimization of conductivity and capacitance.
3Speed
If thicker oxide is deposited over the drift region to reduce gate drain capacitance, then switching speed improves, but breakdown voltage may be affected
Solution Approach 1:
The patent creates terraced oxide structures with different thicknesses at different locations. Thicker oxide is deposited at the body region edges to reduce gate drain capacitance, while the gate area maintains appropriate oxide thickness for breakdown voltage. This spatial differentiation resolves the contradiction between switching speed and breakdown voltage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces gate drain capacitance, enhancing switching speed and frequency of operation while preserving or restoring breakdown voltage, thus addressing the limitations of existing SiC Power MOSFET designs.
Implementation Method 1
The gate drain capacitance of a Power MOSFET consists of a 'MOS capacitance' defined by the gate overlap over the drain region between the P-Wells
Implementation Method 2
forming P-type wells (Body) regularly spaced in the N-type doped drift layer, placing N-type ion implanted layers (source) inside of the P-wells
Data Source
AI summary
A Vertical Multiple Implanted Silicon Carbide Power MOSFET (VMIMOSFET) includes a first conductivity semiconductor substrate, a first conductivity semiconductor drift layer on the top of the substrate, a multitude of second conductivity layers implanted in the drift layer. The body layer is where the channel is formed. A first conductivity source layer is interspaced appropriately inside of the second conductivity layers. A gate oxide of a certain thickness and another oxide of a different thickness, a greater thickness than the gate oxide, placed in between the body layers but in such way that its shape does not distort the gate oxide in the channel. A charge compensated body layer of the second conductivity formed outside of the channel region and only at specific high electric field locations in the structure. The device and the manufacturing method deliver a power SiC MOSFET with increased frequency of operation and reduced switching losses.