Self-Aligned SiC Power MOSFET Layout for Uniform Channel Length
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Solution Overview
Problem
Existing silicon carbide (SiC) power MOSFETs face reliability issues due to lithographic misalignment between p-well and N+ source regions, leading to asymmetric MOS channel lengths, increased ON resistance, and potential parasitic transistor activation during extreme conditions.
Innovation Solution
A self-aligned manufacturing process is employed, involving multiple hard mask layers and etching steps to form self-aligned N+ source regions and P+ plug regions, along with source trenches, to ensure precise alignment and remove parasitic N+ source regions, thereby improving channel length uniformity and preventing parasitic transistor activation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If two separate masking steps are used to form p-well and N+ source regions, then the manufacturing process is simpler, but lithographic misalignment occurs resulting in asymmetric MOS channel lengths and increased ON resistance
Solution Approach 1:
The patent merges the formation of p-well and N+ source region masking into a single self-aligned process. The N+ source region mask is positioned using the p-well structure as a reference, eliminating the need for separate masking steps and ensuring precise alignment between the two regions, thereby achieving uniform MOS channel lengths.
Solution Approach 2:
The p-well structure serves as a self-aligning reference for positioning the N+ source region mask. The mask is designed to automatically align with the p-well boundaries, allowing the structure itself to define the precise location of the N+ source region without requiring additional alignment steps or complex masking procedures.
2Manufacturing precision
If channel length is reduced to compensate for misalignment, then ON resistance decreases, but threshold voltage degradation and short-channel effects increase
Solution Approach 1:
The patent introduces a spacer layer (referred to as 'p-well spacer' in the claims) that acts as a physical buffer between the p-well and N+ source region. This spacer defines the MOS channel length with high precision, allowing the channel length to be controlled by the spacer thickness rather than by misalignment-prone lithographic processes, thereby maintaining threshold voltage stability even with sub-micron channel lengths.
3Manufacturing precision
If self-aligned process with multiple hard mask layers is used, then MOS channel length uniformity improves, but manufacturing process complexity increases
Solution Approach 1:
The patent forms the hard mask layers and spacers in advance, before the final N+ source region implantation. The p-well spacer is deposited and patterned beforehand to define the precise location where the N+ source region will be formed. This preliminary structuring ensures that when the N+ implantation occurs, the alignment is already established, simplifying the overall process despite the additional initial steps.
4Reliability
If parasitic N+ source regions are removed to prevent parasitic transistor activation, then device reliability improves, but additional manufacturing steps are required
Solution Approach 1:
The patent selectively removes parasitic N+ source regions that form in peripheral areas where they are not needed. By extracting only these harmful regions while preserving the N+ source regions in active device areas, the patent prevents parasitic transistor activation without requiring a complete redesign of the N+ source formation process. This targeted removal approach minimizes additional process complexity while achieving the reliability improvement.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The process enhances MOS channel density, reduces ON resistance, increases effective field-effect mobility, and improves device reliability by eliminating misalignment-induced asymmetry and parasitic transistor effects, resulting in higher dV/dt rating and reduced switching losses.
Implementation Method 1
A self-aligned manufacturing process is employed, involving multiple hard mask layers and etching steps to form self-aligned N+ source regions and P+ plug regions
Implementation Method 2
depositing a first hard mask layer on the SiC substrate and patterning the first hard mask layer
Implementation Method 3
performing an etch back of at least a portion of the second hard mask layer to form a sidewall spacer
Data Source
AI summary
An embodiment relates to a method obtaining a silicon carbide wafer comprising a first conductivity type substrate and a first conductivity type drift layer, forming a second conductivity type first well region within the first conductivity type drift layer, forming a first conductivity type source region within the second conductivity type first well region, forming a second conductivity type plug region under the first conductivity type source region, forming a gate oxide layer, forming a patterned gate metal layer, depositing an interlevel dielectric (ILD) layer, forming a first patterned mask layer on top of the ILD layer, and etching the ILD layer and the first conductivity type source region using the first patterned mask layer, and forming a silicide layer, wherein the silicide layer is in contact with a vertical sidewall of the first conductivity type source region and at-least one second conductivity type region.