SiC MOSFET Channel Buffer Region for Leakage Suppression
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Solution Overview
Problem
Silicon carbide (SiC) MOSFETs face challenges in achieving a balance between high-temperature operation and low channel resistance due to degraded channel mobility and increased leakage current at high temperatures, especially when the channel length is shortened to 1 μm or less, leading to decreased breakdown voltage.
Innovation Solution
A semiconductor device design incorporating a silicon carbide substrate with a high-concentration p-type fourth SiC region acting as a channel buffer, which suppresses leakage current and maintains stable breakdown voltage at high temperatures by forming a channel buffer region with an impurity concentration at least two orders of magnitude higher than the p well region, and a specific fabrication process involving ion implantation to define the regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the channel length is shortened to 1 μm or less to reduce channel resistance, then the on resistance decreases, but the leakage current increases at high temperatures causing breakdown voltage to decrease
Solution Approach 1:
The patent applies local quality by creating a channel buffer region with specifically engineered impurity concentration (1×10^18 to 1×10^19 atoms/cm³) that differs from both the p well region and the channel region. This localized modification of impurity concentration in the channel buffer region suppresses leakage current at high temperatures while allowing the channel length to be shortened for low on-resistance operation.
Solution Approach 2:
The patent changes the impurity concentration parameter in the channel buffer region to a specific range (1×10^18 to 1×10^19 atoms/cm³) that is at least one order of magnitude higher than the p well region but controlled to be at most 10 times the channel region concentration. This parameter optimization enables the channel length to be reduced to 1 μm or less while maintaining breakdown voltage through suppressed leakage current.
2Manufacturing precision
If the channel length is shortened to reduce on resistance, then the device can operate with lower resistance, but channel mobility is degraded by interface states causing higher on resistance
Solution Approach 1:
The patent applies local quality by modifying only the channel buffer region with elevated impurity concentration while keeping the channel region and other areas unchanged. This localized approach improves channel mobility by reducing interface state effects in the buffer region without affecting the channel formation quality, enabling short channel lengths to achieve low on-resistance.
Solution Approach 2:
The patent applies preliminary action by pre-forming the channel buffer region with appropriate impurity concentration before channel formation. This preliminary modification of the buffer region reduces interface state density that would otherwise degrade channel mobility, allowing the subsequent channel to be formed with optimal characteristics even at 1 μm or less length.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces on-resistance and maintains high breakdown voltage even at channel lengths of 1 μm or less, ensuring stable operation at high temperatures by suppressing leakage current and optimizing impurity concentrations and region lengths.
Implementation Method 1
a fourth SiC region (channel buffer region) having an impurity concentration higher than that of the first SiC region is formed between the first SiC region and the second SiC region
Data Source
AI summary
One embodiment of a semiconductor device includes: a silicon carbide substrate including first and second principal surfaces; a first-conductive-type silicon carbide layer on the first principal surface; a second-conductive-type first silicon carbide region at a surface of the first silicon carbide layer; a first-conductive-type second silicon carbide region at the surface of the first silicon carbide region; a second-conductive-type third silicon carbide region at the surface of the first silicon carbide region; a second-conductive-type fourth silicon carbide region formed between the first silicon carbide region and the second silicon carbide region, and having an impurity concentration higher than that of the first silicon carbide region; a gate insulator; a gate electrode formed on the gate insulator; an inter-layer insulator; a first electrode connected to the second silicon carbide region and the third silicon carbide region; and a second electrode on the second principal surface.