SiC MOSFET Channel Edge Segmentation for Conduction Loss Reduction

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Solution Overview

Problem

Conventional semiconductor devices, such as MOSFETs, experience high on-state resistance due to internal components, leading to inefficiencies and increased costs in power conversion systems, particularly in devices like SiC MOSFETs where channel resistance contributes significantly to conduction losses.

Innovation Solution

The design incorporates a channel region with a non-uniform edge, featuring alternating longer and shorter portions, which reduces the effective channel length and channel resistance without compromising blocking voltage, achieved through a specific fabrication method involving a mask with a non-uniform periphery and conformal film layer processing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of energy

If a conventional uniform channel length is used, then the device structure is simple and easy to manufacture, but the on-state resistance is high leading to increased conduction losses

Engineering Contradiction:
Improveconduction lossesVSAvoidchannel structure complexity
Core Design Contradiction:
Loss of energyVSDevice complexity

Solution Approach 1:

The channel region is segmented into multiple sections with different lengths along its width, creating alternating longer and shorter portions. This segmentation reduces the effective channel length and overall channel resistance, thereby decreasing conduction losses while distributing the resistance reduction across different spatial zones

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different portions of the channel region are given different local properties by varying the channel length in specific areas. The alternating longer and shorter portions create localized resistance variations that collectively reduce the total on-state resistance without uniformly simplifying the entire structure

Inventive Principle:
Principle #3Local quality

2Loss of energy

If the channel length is reduced to lower resistance, then the on-state resistance decreases, but the blocking voltage capability may be compromised

Engineering Contradiction:
Improveconduction lossesVSAvoidblocking voltage capability
Core Design Contradiction:
Loss of energyVSReliability

Solution Approach 1:

The channel is divided into alternating longer and shorter portions, where the longer portions maintain adequate channel length for voltage blocking while the shorter portions reduce resistance. This segmented approach allows simultaneous optimization of both conduction and blocking characteristics

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different regions of the channel are assigned different lengths to fulfill different functional requirements: longer portions provide voltage blocking capability while shorter portions contribute to resistance reduction, achieving local optimization of both parameters

Inventive Principle:
Principle #3Local quality

3Loss of energy

If a non-uniform channel edge is implemented, then the effective channel length is reduced improving conduction, but the fabrication process becomes more complex

Engineering Contradiction:
Improveconduction lossesVSAvoidfabrication process simplicity
Core Design Contradiction:
Loss of energyVSEase of manufacture

Solution Approach 1:

A mask with a non-uniform periphery is used in the implantation process to predefine the alternating longer and shorter channel portions. This preliminary patterning action enables the non-uniform channel structure to be created in a single fabrication step rather than requiring multiple complex processing steps

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS9716144B2Semiconductor devices having channel regions with non-uniform edge
Publication Date: 2017.07.25 GENERAL ELECTRIC CO
  • US9716144B2 patent drawing
  • US9716144B2 patent drawing
  • US9716144B2 patent drawing

AI summary

A semiconductor device may include a drift region having a first conductivity type, a source region having the first conductivity type, and a well region having a second conductivity type disposed adjacent to the drift region and adjacent to the source region. The well region may include a channel region that has the second conductivity type disposed adjacent to the source region and proximal to a surface of the semiconductor device cell. The channel region may include a non-uniform edge that includes at least one protrusion.