SiC MOSFET Channel Structure for Low On-Resistance and High Vth

Solution Overview

Problem

Silicon carbide MOSFETs face challenges with high specific on-resistance due to non-ideal MOS interfaces, leading to inferior short circuit characteristics and reliability issues compared to silicon devices, primarily because the channel contributes a larger percentage of the device on-resistance and requires high gate overdrive voltage.

Innovation Solution

The improved Silicon Carbide MOSFET structure incorporates a heavily doped substrate, a lightly doped epitaxial layer, and strategically formed accumulation and inversion mode regions, with a source region, to reduce the inversion mode channel length and increase threshold voltage, thereby enhancing channel electrostatic integrity and lowering specific on-resistance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of energy

If the channel length is reduced to lower specific on-resistance, then the device on-resistance decreases, but the short circuit characteristics deteriorate

Engineering Contradiction:

Improvespecific on-resistanceVSAvoidshort circuit characteristics

Core Design Contradiction:

Loss of energyVSReliability

Solution Approach 1:

The patent applies local quality by creating distinct accumulation mode and inversion mode regions with different dopant concentrations within the channel. The accumulation mode region has higher dopant concentration to reduce resistance, while the inversion mode region has lower dopant concentration to maintain electrostatic control and short circuit characteristics. This spatial differentiation of doping profiles allows simultaneous optimization of both on-resistance and short circuit performance.

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The patent utilizes parameter changes by varying the dopant concentration profile along the channel length. The accumulation mode region employs higher dopant concentration (1E16 to 1E18 atoms/cm³) compared to the inversion mode region (1E15 to 1E17 atoms/cm³). This parameter variation enables the channel to achieve low on-resistance while maintaining proper electrostatic control and short circuit behavior.

Inventive Principle:

Principle #35Parameter changes

2Loss of energy

If high gate overdrive voltage is used to maintain low specific on-resistance, then the device on-resistance decreases, but the dielectric electric field increases reducing reliability

Engineering Contradiction:

Improvespecific on-resistanceVSAvoiddielectric electric field

Core Design Contradiction:

Loss of energyVSReliability

Solution Approach 1:

The patent changes the dopant concentration parameter in the channel regions to achieve low specific on-resistance at reduced gate overdrive voltages. The accumulation mode region with higher dopant concentration provides low resistance conduction paths, while the inversion mode region maintains proper threshold voltage control. This parameter optimization reduces the required gate overdrive voltage, thereby reducing the dielectric electric field and improving reliability.

Inventive Principle:

Principle #35Parameter changes

3Loss of energy

If the MOS interface is improved to reduce channel resistance contribution, then the specific on-resistance decreases, but the device complexity increases

Engineering Contradiction:

Improvespecific on-resistanceVSAvoidMOS interface structure

Core Design Contradiction:

Loss of energyVSDevice complexity

Solution Approach 1:

The patent applies local quality by creating distinct accumulation mode and inversion mode regions with different dopant concentrations within the channel. The accumulation mode region has higher dopant concentration to reduce resistance, while the inversion mode region has lower dopant concentration to maintain electrostatic control and short circuit characteristics. This spatial differentiation of doping profiles allows simultaneous optimization of both on-resistance and short circuit performance.

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The patent utilizes parameter changes by varying the dopant concentration profile along the channel length. The accumulation mode region employs higher dopant concentration (1E16 to 1E18 atoms/cm³) compared to the inversion mode region (1E15 to 1E17 atoms/cm³). This parameter variation enables the channel to achieve low on-resistance while maintaining proper electrostatic control and short circuit behavior.

Inventive Principle:

Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This design effectively reduces specific on-resistance while maintaining good channel electrostatic integrity, improving short circuit performance and reliability by optimizing dopant concentrations and region configurations.

Implementation Method 1

a heavily doped substrate, a lightly doped epitaxial layer, and strategically formed accumulation and inversion mode regions

Methodology Applied

Scientific EffectDoping: Dopants

Implementation Method 2

enhancing channel electrostatic integrity and lowering specific on-resistance

Methodology Applied

Scientific EffectElectrostatic control: Electric Field

Data Source

PatentUS11776994B2SiC MOSFET with reduced channel length and high V<sub>th</sub>

Publication Date: 2023.10.03 ALPHA & OMEGA SEMICON INT LP

AI summary

A silicon carbide MOSFET device and method for making thereof are disclosed. The silicon carbide MOSFET device comprises a substrate heavily doped with a first conductivity type and an epitaxial layer lightly doped with the first conductivity type. A body region of a second conductivity type opposite the first is formed in epitaxial layer and an accumulation mode region of the first conductivity type is formed in the body region and an inversion mode region of the second conductivity type formed in the body region. The accumulation mode region is located between the inversion mode region and a junction field effect transistor (JFET) region of the epitaxial layer.