SiC MOSFET Gate Protection via Integrated Clamping Circuit
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Solution Overview
Problem
Silicon carbide (SiC) semiconductor devices face risks of damage from gate overvoltage and reduced tolerance to electrostatic discharge due to low specific on-resistance and small input capacitance, with existing protection methods increasing complexity, stray inductance, and leakage current issues.
Innovation Solution
Integration of a bidirectional voltage clamp clamper circuit in the SiC semiconductor device to clamp both positive and negative overvoltages between the gate and source, utilizing a p-floating region with specific doping profiles and ohmic contacts to suppress voltages below breakdown levels and enhance ESD tolerance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a polysilicon Zener diode is additionally disposed to protect the gate, then gate protection against overvoltage and ESD is improved, but packaging complexity increases and stray inductance is induced
Solution Approach 1:
The protection function is merged into the MOSFET structure by integrating the p-floating region directly into the semiconductor substrate. This eliminates the need for separate Zener diode components and their associated packaging, while providing both overvoltage protection and ESD tolerance through the integrated clamp circuit.
Solution Approach 2:
The p-floating region acts as an intermediary structure that provides voltage clamping protection. By positioning this region between the gate and source with specific doping profiles, it creates a controlled breakdown path that protects the gate oxide without requiring external protection components.
2Reliability
If a bidirectional voltage clamp is integrated with specific doping profiles, then overvoltage protection and ESD tolerance are improved, but device structure becomes more complex
Solution Approach 1:
The p-floating region structure serves multiple functions simultaneously: it provides overvoltage protection through voltage clamping, offers ESD tolerance through controlled breakdown, and maintains low leakage current through optimized doping profiles. This multi-functional design eliminates the need for separate protection circuits for each function.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Effectively prevents device damage from overvoltages and improves ESD tolerance with low leakage current and stability across temperatures, reducing packaging complexity and stray inductance compared to prior art.
Implementation Method 1
a bidirectional voltage clamp is disposed on the first surface, and includes a first terminal connected to the gate and a second terminal connected to the source
Implementation Method 2
utilizing a p-floating region with specific doping profiles and ohmic contacts to suppress voltages below breakdown levels
Implementation Method 3
Due to the presence of a wide energy gap of silicon carbide, given the same drain-to-source voltage (VDS) specification, a specific on-resistance (ron, sp=on resistance*active area) of a silicon carbide metal-oxide-semiconductor field-effect transistor
Implementation Method 4
because a SiC MOSFET further has a low specific on-resistance and a small input capacitance, the tolerance of the SiC MOSFET against electrostatic discharge (ESD) taking place between the gate and the source is also reduced
Data Source
AI summary
The present invention provides a silicon carbide (SiC) semiconductor device integrating a metal-oxide-semiconductor field-effect transistor (MOSFET) and a bidirectional voltage clamping circuit. An object of protecting a device is achieved by using the simple structure above, effectively preventing device damage that may be caused by a positive overvoltage and a negative overvoltage between a gate and a source.