SiC MOSFET Contact Region Doping for Lower ON Resistance
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Solution Overview
Problem
In semiconductor devices using silicon carbide (SiC), the low diffusion coefficient of impurity atoms leads to increased contact resistance and ON resistance due to mask alignment deviations and carrier compensation in the p+ base contact and n+ source regions.
Innovation Solution
A semiconductor device structure with a drift layer, current spreading region, base region, and electrode contact region of specific impurity densities, where the base contact region has at least twice the impurity density of the electrode contact region, is epitaxially grown and ion-implanted to prevent mask alignment deviations and reduce contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If double ion implantation is used to form the p-type well region and n+ source region in SiC MOSFET, then the source region can be formed, but crystal defects are induced which cause increased contact resistance and ON resistance
Solution Approach 1:
The patent segments the impurity addition process into two distinct stages: first forming the p-type well region with moderate impurity concentration, then selectively forming the n+ source region with high impurity concentration only in specific areas. This segmentation avoids the crystal damage caused by attempting to form both regions simultaneously through double ion implantation.
Solution Approach 2:
The patent performs preliminary formation of the p-type well region before selectively forming the n+ source region. By establishing the well region first with controlled impurity concentration, the substrate is prepared to receive subsequent high-concentration source region impurities without excessive crystal damage, thereby reducing contact resistance.
2Manufacturing precision
If selective ion implantation is used to form the n-type source region and then p-type base contact region, then both regions can be formed, but mask alignment deviations cause overlapping which increases resistance due to carrier compensation
Solution Approach 1:
The patent applies local quality by giving the base contact region a significantly higher impurity density (at least twice that of the source region) in the overlapping area. This localized high-concentration doping ensures that even if mask alignment deviations cause overlap, the base contact region maintains low resistance due to its superior impurity concentration, compensating for the carrier compensation effect.
3Ease of manufacture
If the impurity densities of source region and base contact region are kept around the same level, then both regions can be formed with similar doping, but the overlapping portion has higher resistance due to carrier compensation
Solution Approach 1:
The patent fundamentally changes the impurity density parameter between the base contact region and source region. The base contact region is doped with impurity density at least twice that of the source region, creating a parameter difference that ensures low contact resistance even in overlapping areas, while the source region maintains its required electrical characteristics.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This structure effectively suppresses the increase in ON resistance and forward voltage of the body diode, preventing carrier compensation and improving the semiconductor device's performance by maintaining a higher impurity density in the base contact region compared to the source region.
Implementation Method 1
the base contact region has at least twice the impurity density of the electrode contact region, is epitaxially grown and ion-implanted to prevent mask alignment deviations and reduce contact resistance
Implementation Method 2
A semiconductor device structure with a drift layer, current spreading region, base region, and electrode contact region of specific impurity densities, where the base contact region has at least twice the impurity density of the electrode contact region, is epitaxially grown
Data Source
AI summary
A semiconductor device includes a current spreading region of the first conductivity type provided on a drift layer and having a higher impurity density than the drift layer; a base region of a second conductivity type provided on the current spreading region; a base contact region of the second conductivity type provided in a top part of the base region and having a higher impurity density than the base region; and an electrode contact region of the first conductivity type provided in a top part of the base region that is laterally in contact with the base contact region, the electrode contact region having a higher impurity density than the drift layer, wherein a density of a second conductivity type impurity element in the base contact region is at least two times as much as a density of a first conductivity type impurity element in the electrode contact region.