SiC Power MOSFET Saturation Current Clamp for Short-Circuit Withstand
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Solution Overview
Problem
Conventional silicon carbide (SiC) power MOSFETs have a short short-circuit withstand time, leading to potential device failure during high power applications, and attempts to increase this time by reducing drain saturation current result in increased on-state resistance and undesired short-channel effects.
Innovation Solution
Incorporating a saturation current clamp (SCC) using a depletion-mode JFET with shorted gate and source terminals, which provides non-linear resistance to limit short-circuit current and increase short-circuit withstand time with minimal increase in on-state resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of stationary object
If drain saturation current is reduced to increase short-circuit withstand time, then short-circuit withstand time is improved, but on-state resistance increases and short-channel effects worsen
Solution Approach 1:
The patent introduces a saturation current clamp (SCC) as an intermediary component between the gate and the active region. This SCC acts as a mediator that limits the maximum current through non-linear resistance without requiring reduction of the main channel current, thereby extending short-circuit withstand time while preserving the device's normal operating characteristics and avoiding short-channel effects.
Solution Approach 2:
The patent utilizes parameter changes by implementing a depletion-mode JFET whose resistance varies non-linearly with applied voltage. At normal operating voltages, the JFET maintains low resistance to minimize on-state impact. During short-circuit conditions, the voltage across the JFET increases, causing its resistance to increase non-linearly and clamp the current, thus extending withstand time without degrading normal device performance.
2Duration of action of stationary object
If saturation current clamp is added to increase short-circuit withstand time, then short-circuit withstand time is improved, but device complexity increases
Solution Approach 1:
The patent merges the saturation current clamp function directly into the existing device structure by integrating a depletion-mode JFET within the same semiconductor substrate. The JFET shares common regions with the main MOSFET structure, and both devices operate from the same gate terminal, effectively combining multiple functions into a single integrated device rather than adding separate components.
Solution Approach 2:
The gate terminal serves multiple functions: it controls the main MOSFET channel for normal switching operation and simultaneously controls the depletion-mode JFET to provide saturation current clamping during fault conditions. This multi-functionality allows a single control terminal to manage both normal operation and protective functions, reducing the need for additional control circuitry.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The SCC effectively increases short-circuit withstand time by about 4 times with only a 5-8% increase in on-state resistance, reducing the risk of device failure during high power applications.
Implementation Method 1
The SCC operates with a substantially non-linear resistance, which increases with increasing current level
Implementation Method 2
a depletion-mode JFET having an N-type 'channel' region, which extends between an N+ source region and P-type (or N-type) base region
Data Source
AI summary
A power device includes a packaged semiconductor switch containing first and second series-connected insulated-gate transistors, first and second control terminals electrically connected to the first and second insulated-gate transistors, respectively, first and second current carrying terminals electrically connected to the first and second insulated-gate transistors, respectively, and a voltage-monitoring terminal electrically connected to an internal node shared by first and second current carrying regions within the first and second insulated-gate transistors, respectively. The first and second control terminals can be electrically connected to a gate of the first insulated-gate transistor and a gate of the second insulated-gate transistor, respectively; and the first and second current carrying terminals can be electrically connected to a source of the first insulated-gate transistor and a drain (or collector) of the second insulated-gate transistor. The voltage-monitoring terminal is electrically connected to a drain of the first insulated-gate transistor and a source (or emitter) of the second insulated-gate transistor.