SiC Power MOSFET with Defect-Free Substrate
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor devices, particularly power MOSFETs, face challenges in achieving high-breakdown voltage and low RDSON while maintaining reliability in harsh environments due to defects in SiC substrates and radiation exposure, which increases manufacturing costs and defect densities.
Innovation Solution
The development of a method to form a substantially defect-free SiC substrate using a sacrificial heteroepitaxy interface and direct wafer bonding techniques, which confines defects to sacrificial layers and removes them, enabling the creation of high-breakdown voltage trench gate power MOSFETs with reduced RDSON and enhanced radiation hardness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If SiC layer is formed on Si substrate, then high breakdown voltage and high power density are achieved, but defect density increases due to heterointerface between dissimilar materials
Solution Approach 1:
A buffer layer is introduced between the SiC layer and Si substrate to act as an intermediary that reduces lattice mismatch and thermal expansion differences. This buffer layer absorbs stress and prevents defect propagation from the heterointerface, thereby maintaining high breakdown voltage while reducing defect density in the SiC layer.
Solution Approach 2:
The device structure is segmented into distinct layers with different functions: Si substrate for mechanical support, buffer layer for stress management, and SiC layer for high-voltage operation. This segmentation allows each layer to be optimized independently, reducing the negative impact of the heterointerface while preserving the high breakdown voltage capability.
2Ease of manufacture
If conventional SiC substrate manufacturing is used, then manufacturing cost is reduced, but radiation hardness decreases leading to higher failure rates in harsh environments
Solution Approach 1:
The manufacturing process parameters are changed to grow SiC layers with specific crystal orientations and doping profiles that enhance radiation hardness. By controlling epitaxial growth conditions and layer structure, the device achieves improved resistance to radiation-induced failures while maintaining cost-effective manufacturing through standardized processes.
3Ease of manufacture
If high defect density SiC substrates are used, then manufacturing cost is low, but device reliability and yield decrease
Solution Approach 1:
The defective SiC layer containing heterointerface defects is completely removed through selective etching, and only the high-quality SiC layer grown on the buffer layer is retained. This extraction of defective material eliminates the source of device failures and yield losses, while the buffer layer remains to support the high-voltage device structure.
Solution Approach 2:
The buffer layer is formed in advance before growing the SiC layer, creating a pre-prepared substrate that minimizes defect formation during SiC epitaxial growth. This preliminary action of preparing the buffer layer with appropriate thickness and composition prevents defect generation at the interface, ensuring high yield from the outset.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in semiconductor devices with improved breakdown voltage, reduced RDSON, and increased radiation hardness, achieving 1200V blocking capability with RDSON of 90 milliohms at 40A, suitable for aerospace and deep space applications while maintaining low manufacturing costs.
Implementation Method 1
The SiC semiconductor layer or substrate provides some useful advantages, such as high breakdown voltage, high speed, reduced switching losses, high power density, high temperature, better heat dissipation, and increased bandwidth capability.
Implementation Method 2
The heterointerface causes stress during temperature cycling and leads to defects in the SiC layer
Implementation Method 3
The development of a method to form a substantially defect-free SiC substrate using a sacrificial heteroepitaxy interface and direct wafer bonding techniques
Data Source
AI summary
A semiconductor device has a substrate. The substrate can be multiple layers. A first semiconductor layer made of a first semiconductor material is disposed over the substrate. The first semiconductor material can be substantially defect-free silicon carbide. A second semiconductor layer made of a second semiconductor material dissimilar from the first semiconductor material is disposed over the first semiconductor layer. The second semiconductor material is silicon. A third layer can be disposed between the first semiconductor layer and second semiconductor layer. A semiconductor device is formed in the second semiconductor layer. The semiconductor device can be a power MOSFET or diode. The second semiconductor layer with the electrical component provides a first portion of a breakdown voltage for the semiconductor device and the first semiconductor layer and substrate provide a second portion of the breakdown voltage for the semiconductor device.