SiC MOSFET Double Trench Gate Structure for On-Resistance Reduction
Solution Overview
Problem
Current semiconductor devices, particularly vertical-type MOSFETs, face challenges in reducing on-resistance due to limitations in trench gate structure design and impurity concentration distribution, which affects their performance and reliability.
Innovation Solution
The semiconductor device incorporates a silicon carbide layer with a double trench structure and specific impurity concentration profiles, including a p-type electric field relaxation region and a buried interlayer insulating layer, to enhance the channel area per unit area and reduce on-resistance, while also improving the reliability of the gate insulating layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a simple single trench structure is used, then device complexity is low, but on-resistance cannot be sufficiently reduced
Solution Approach 1:
The patent segments the semiconductor layer into distinct regions with different impurity concentrations: a high-concentration region for channel formation and a low-concentration electric field relaxation region at the gate insulating layer interface. This segmentation allows the simple trench gate structure to achieve low on-resistance through optimized impurity distribution without increasing structural complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces the on-resistance of the MOSFET by increasing the channel area and relaxing the electric field during off-operation, leading to improved performance and reliability.
Implementation Method 1
a fourth silicon carbide region of p-type located between the second trench and the first silicon carbide region, the fourth silicon carbide region being located between the second trench and the second silicon carbide region, and the fourth silicon carbide region having higher p-type impurity concentration than the second silicon carbide region
Data Source
AI summary
A semiconductor device according to an embodiment includes: a silicon carbide layer having a first plane, a second plane facing the first plane, a first trench, a second trench, an n-type first silicon carbide region, a p-type second silicon carbide region between the first silicon carbide region and the first plane, an n-type third silicon carbide region between the second silicon carbide region and the first plane, and a p-type fourth silicon carbide region between the second trench and the first silicon carbide region; a gate electrode being located in the first trench; a gate insulating layer; a first electrode, a portion of the first electrode being located in the second trench; a second electrode; and an interlayer insulating layer being located between the gate electrode and the first electrode, in which an interface between the first electrode and the interlayer insulating layer is located in the first trench.