SiC MOSFET Dual Source Region for Low On-Resistance
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Solution Overview
Problem
Conventional semiconductor devices using silicon carbide substrates face challenges in reducing on-resistance and achieving stable characteristics due to alignment variations and high JFET resistance, while also struggling with avalanche current and dielectric breakdown issues.
Innovation Solution
The semiconductor device incorporates a silicon carbide substrate with specific impurity concentration layers and regions, including a second source region with higher impurity concentration, a third semiconductor region formed deeper than the first, and a fourth semiconductor region under the first semiconductor region, all formed using ion implantation masks to reduce on-resistance and improve avalanche reliability and dielectric breakdown resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional MOSFET structure is used with silicon carbide substrate, then device can be manufactured with standard process, but on-resistance is high and characteristics are unstable due to alignment variations
Solution Approach 1:
The source region is divided into two separate source regions (first source region and second source region) with different impurity concentrations and depths. This segmentation allows independent optimization of each source region's function, reducing the impact of alignment variations on overall device performance and stabilizing characteristics.
Solution Approach 2:
Different regions of the source are given different impurity concentrations and depths. The first source region has lower impurity concentration and shallower depth, while the second source region has higher impurity concentration and greater depth. This local quality differentiation optimizes both low-on-resistance and alignment tolerance in specific areas.
2Manufacturing precision
If single source region configuration is used, then device structure is simple, but on-resistance cannot be sufficiently reduced
Solution Approach 1:
The source region is segmented into two distinct regions with different impurity concentrations and depths, enabling independent control of on-resistance characteristics while maintaining a manageable device structure.
Solution Approach 2:
The dual source region structure introduces depth as an additional dimension for resistance control. By varying both impurity concentration and depth, the invention achieves superior on-resistance control compared to conventional single-layer sources.
3Manufacturing precision
If higher impurity concentration is used in source region, then on-resistance decreases, but avalanche current control deteriorates and dielectric breakdown resistance decreases
Solution Approach 1:
Different impurity concentrations are assigned to different source regions and depths. The first source region has lower impurity concentration for avalanche control, while the second source region has higher impurity concentration for low on-resistance, achieving both goals simultaneously in different locations.
Solution Approach 2:
The source region is segmented into two parts with different impurity concentrations. This segmentation allows the device to exhibit low on-resistance through the high-concentration second source region while maintaining avalanche control through the lower-concentration first source region.
4Reliability
If conventional single-layer source structure is used, then manufacturing process is simple, but parasitic npn transistor operation cannot be suppressed
Solution Approach 1:
The source region is segmented into two layers with different impurity concentrations and depths, which suppresses parasitic npn transistor operation by controlling carrier injection and distribution, preventing unwanted transistor activation.
Solution Approach 2:
The invention changes the impurity concentration parameter across different source regions and depths. This parameter variation suppresses parasitic transistor operation by controlling the electrical characteristics and carrier behavior in the source region.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces on-resistance, stabilizes characteristics, suppresses parasitic npn transistor operation, and enhances dielectric breakdown resistance by controlling avalanche current and impurity concentration layers, resulting in improved reliability and threshold voltage precision.
Implementation Method 1
a second source region of the first conductivity type, formed in the surface layer of the first semiconductor region, farther on an outer side than the first source region, the second source region contacting the first source region and having an impurity concentration higher than that of the first source region
Data Source
AI summary
A semiconductor device includes an n+-type source region having an impurity concentration higher than that of an n-type source region, formed in a surface layer of a p-type SiC layer and a p-type base region, farther on an outer side than the n-type source region, and contacting the n-type source region; an n-type region and an n+-type region having an impurity concentration higher than that of the n−-type SiC layer, formed in a portion of the n−-type SiC layer between p-type base regions and p-type SiC layers; and a second n-type region under the p-type base region and of a size smaller than that of the p-type base region, whereby low on-resistance and precision of the threshold voltage Vth are enhanced, increasing quality and enabling improved resistance to dielectric breakdown of the gate insulating film and resistance to breakdown.