SiC MOSFET Edge Termination for Stable Breakdown Voltage
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional semiconductor devices using silicon carbide (SiC) face instability in breakdown voltage characteristics due to variations in impurity concentration in the p-type region of the junction termination extension (JTE) structure, which affects the edge termination structure and active region.
Innovation Solution
A semiconductor device design with a specific edge termination structure that includes multiple second-conductivity-type semiconductor regions with controlled impurity concentrations, where the closest third second-conductivity-type semiconductor region is electrically connected to the second second-conductivity-type semiconductor region only in specific areas, such as under the gate pad and gate runners, to stabilize breakdown voltage without affecting the active region's impurity concentration and structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional JTE structure with p-type region is used in SiC MOSFET, then breakdown voltage can be sustained, but impurity concentration variations cause instability in breakdown voltage characteristics
Solution Approach 1:
The patent applies local quality by creating distinct regions with different conductivity types and impurity concentrations: n-type regions in the active area, p-type regions in the termination area, and n-type stop regions at the boundary. This localized differentiation allows the device to achieve both high breakdown voltage in the termination region and stable electrical characteristics in the active region, resolving the contradiction between breakdown voltage sustainability and impurity concentration stability.
Solution Approach 2:
The semiconductor device is segmented into functionally distinct regions: an active region with n-type drift layer for current conduction, a termination region with p-type regions for breakdown voltage sustenance, and n-type stop regions at the boundary to prevent depletion layer interaction. This segmentation isolates the impurity concentration variations in the p-type termination region from affecting the active region, thereby maintaining breakdown voltage stability while allowing manufacturing tolerances in the termination area.
2Quantity of substance
If higher current density is used to increase current handling capability, then current capacity improves, but switching speed decreases due to material limits
Solution Approach 1:
The patent changes the material parameter from silicon to silicon carbide, which has fundamentally different electrical properties including higher critical electric field strength and higher saturation velocity. This material parameter change enables the device to achieve both high current density and high switching frequency simultaneously, as SiC can sustain higher electric fields without breakdown and carriers move faster, resolving the contradiction between current capacity and switching speed that plagues conventional silicon devices.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design achieves stable high breakdown voltage characteristics and low ON-resistance, maintaining high breakdown voltage even with variations in impurity concentration, and improves channel mobility by using epitaxial growth for the second-conductivity-type semiconductor layer, reducing interface state density and ON-resistance.
Implementation Method 1
improves channel mobility by using epitaxial growth for the second-conductivity-type semiconductor layer
Data Source
AI summary
In an active region, p+ regions are selectively disposed in a surface layer of an n− drift layer on an n+ semiconductor substrate. A p-base layer is disposed on surfaces of the n− drift layer and the P+ regions, and an MOS structure is disposed on the p-base layer. In another portion of the active region, a p+ region is disposed to be in contact with the source electrode on the p+ regions. In a breakdown voltage structure region (100), a JTE structure having at least a P− region is disposed separately from the P+ regions and the p-base layer, to surround the active region. The P− region is electrically in contact with the P+ region in a portion in which the MOS structure is not formed, in the vicinity of the boundary between the active region and the breakdown voltage structure region.