SiC MOSFET Fan-Out Package for Larger Source Pads and Isolation
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Solution Overview
Problem
Existing semiconductor packages face challenges in achieving efficient electrical and mechanical connections, particularly for silicon carbide (SiC) MOSFET devices, due to limitations in contact size and separation requirements, which affect performance and reliability.
Innovation Solution
A fan-out package design is implemented, utilizing a baseframe with extended gate pads and a redistribution layer to maximize source pad size, coupled with Ag sinter material and mold compound for electrical isolation, and incorporating a heat sink for thermal management, allowing for larger contact sizes and improved electrical isolation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If conventional package design is used, then manufacturing is simpler, but source pad size is limited and electrical performance is reduced
Solution Approach 1:
The gate pad is extended beyond the die perimeter in the lateral dimension, creating a fan-out configuration that increases the effective source pad area without increasing the die size. This dimensional extension allows the source pad to connect to a larger area on the baseframe, improving electrical performance while maintaining a compact die footprint.
Solution Approach 2:
A redistribution layer is introduced as an intermediary between the die pad and the baseframe contact pad. This redistribution layer facilitates the fan-out configuration by routing the gate signal laterally and enabling the extended gate pad to connect to a larger source pad area on the baseframe, thereby increasing the effective contact area without directly modifying the die structure.
2Reliability
If contact size is increased, then electrical resistance is reduced, but separation requirements between gate and source increase
Solution Approach 1:
The gate pad is extended laterally beyond the die perimeter, allowing the gate and source contacts to be separated in the lateral dimension rather than being constrained to vertical separation. This fan-out configuration increases the distance between gate and source contact points while maintaining large contact pad sizes, thereby reducing electrical resistance without compromising isolation.
Solution Approach 2:
The electrical connection path is segmented into distinct regions: the die pad, the redistribution layer, and the baseframe contact pad. This segmentation allows the gate and source signals to be routed through separate paths with adequate spacing, maintaining electrical isolation while enabling large contact areas at each interface for reduced resistance.
3Reliability
If Ag sinter material is used, then electrical conductivity is improved, but manufacturing process complexity increases
Solution Approach 1:
The Ag sinter material is applied to multiple contact pads (gate and source) in a single manufacturing step, combining the electrical connection function for multiple signals into one material deposition and sintering process. This approach improves electrical conductivity at all interfaces while minimizing the number of separate manufacturing steps required.
Solution Approach 2:
The Ag sinter material is applied and sintered to the baseframe contact pads before die attachment. This preliminary action prepares the electrical connection interfaces in advance, allowing for optimized sintering conditions and reducing the complexity of subsequent assembly steps. The pre-sintered contacts are then ready to receive the die in a streamlined process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design enhances electrical performance by maximizing source pad size, reducing resistance, and providing reliable electrical isolation over a wide voltage range, while minimizing hot spots and die corner stresses.
Implementation Method 1
coupling an Ag sinter material on one or more gate pads and one or more source pads of the baseframe, pressure sintering one or more gate pads and one or more source pads of one or more semiconductor die with the Ag sinter material
Implementation Method 2
A heat sink may be coupled directly to the one or more semiconductor die through a die adhesive material
Data Source
AI summary
A semiconductor package is disclosed. Specific implementations of a semiconductor package may include: one or more semiconductor die coupled between a baseframe and a clip, the baseframe including a gate pad of the baseframe coupled with a gate pad of the one or more semiconductor die, and a source pad of the baseframe coupled with a source pad of the one or more semiconductor die, where the gate pad of the baseframe extends beyond a perimeter of the one or more semiconductor die.