SiC MOSFET Gate Insulation Field Oxide Film Design
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Solution Overview
Problem
Power semiconductor devices using silicon carbide MOSFETs face challenges with high-speed switching, leading to increased conduction and switching losses, and potential dielectric breakdown due to high electric fields in the gate insulating film, especially when switching from ON to OFF states, resulting in voltage fluctuations that can exceed safe limits.
Innovation Solution
The design incorporates a semiconductor substrate with a drift layer, cell regions, well regions, and a field oxide film to manage displacement currents, reducing the electric field on the gate insulating film by using thicker field oxide films and strategic contact holes to distribute displacement currents effectively, thereby preventing dielectric breakdown.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the MOSFET is switched at high speed (high dV/dt), then switching loss is reduced, but displacement current generates high voltage in the P well which can cause dielectric breakdown of the gate insulating film
Solution Approach 1:
A field plate structure is introduced as an intermediary element between the gate electrode and the P well region. The field plate is electrically connected to the gate electrode and extends over the P well region, acting as a mediator to distribute and control the electric field. This intermediary structure prevents direct high electric field concentration at the gate insulating film-P well interface, thereby avoiding dielectric breakdown while maintaining high-speed switching capability.
Solution Approach 2:
The invention changes the electrical parameters of the P well region by introducing a field plate connection that modifies the potential distribution. The field plate structure alters the electric field parameters in the region, distributing the voltage stress more evenly and preventing the formation of excessive electric fields that would cause breakdown during high-dV/dt switching operations.
2Device complexity
If the P well area under the gate pad is large, then the MOSFET cell structure is simplified, but resistance in the P well increases causing higher voltage generation during displacement current flow
Solution Approach 1:
The field plate serves as an intermediary conductive structure that provides an additional current path for displacement current. By extending the field plate over the large-area P well region, it creates multiple parallel current paths, effectively reducing the resistance in the P well region without requiring the P well area to be reduced, thus maintaining both structural simplicity and voltage control stability.
3Loss of energy
If conventional Si-MOSFET operates at high voltage (1 kV or more), then conduction loss increases greatly, but Si-IGBT can handle high voltage with lower conduction loss at the cost of slower switching speed
Solution Approach 1:
The invention utilizes silicon carbide material to change the fundamental electrical parameters of the semiconductor device. Silicon carbide enables the MOSFET to operate at high voltages (1 kV or more) with low conduction loss while maintaining unipolar operation characteristics that provide fast switching speeds, effectively resolving the trade-off between conduction loss and switching speed that plagues conventional silicon-based devices.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration allows for high-speed switching with reduced conduction and switching losses while maintaining a safe electric field below 3 MV/cm, enhancing the reliability and longevity of the power semiconductor device.
Implementation Method 1
a displacement current is generated on a drain electrode side and a source electrode side respectively through a capacity of a depletion layer which is formed between the P well and an N-drain layer
Data Source
AI summary
In a semiconductor device according to the present invention, a p-type well region disposed in an outer peripheral portion of the power semiconductor device is divided into two parts, that is, an inside and an outside, and a field oxide film having a greater film thickness than the gate insulating film is provided on a well region at the outside to an inside of an inner periphery of the well region. Therefore, it is possible to prevent, in the gate insulating film, a dielectric breakdown due to the voltage generated by the flow of the displacement current in switching.